JPS5767331A - Bias varying circuit - Google Patents

Bias varying circuit

Info

Publication number
JPS5767331A
JPS5767331A JP55143320A JP14332080A JPS5767331A JP S5767331 A JPS5767331 A JP S5767331A JP 55143320 A JP55143320 A JP 55143320A JP 14332080 A JP14332080 A JP 14332080A JP S5767331 A JPS5767331 A JP S5767331A
Authority
JP
Japan
Prior art keywords
ratio
channel
trs
bias
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55143320A
Other languages
Japanese (ja)
Other versions
JPH0133974B2 (en
Inventor
Yasoji Suzuki
Kenji Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55143320A priority Critical patent/JPS5767331A/en
Priority to US06/295,825 priority patent/US4464587A/en
Publication of JPS5767331A publication Critical patent/JPS5767331A/en
Publication of JPH0133974B2 publication Critical patent/JPH0133974B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To stabilize the operation point of an output amplitude to facilitate controlling the output amplitude, by providing plural IG-IFT circuits, which are controlled by plural control signals respectively, at respective bias supply points of a MOS gate part to very the bias. CONSTITUTION:A P channel transistor TR16 and an N channel TR17 are provided in both ends of a MOS inverter 11, and their gates are controlled by a control signal input terminal Cont1, and gates of a P channel TR18 and an N channel TR19 provided between points 12 and 13 are controlled by a control signal input terminal Cont2. Voltages of control terminals 1 and 2 are so determined that the ratio of TRs 16 and 18 is 1:4 when the point 12 is set to 4V and the ratio of TRs 17 and 19 is 1:4 when the point 13 is set to 1V, and thus, a range of the bias is determined, and an amplitude corresponding to an input IN is obtained in an output Out. The gm ratio of TR16 and 18, and the gm ratio of TRs 17 and 19 are determined by voltages of control terminals 1 and 2.
JP55143320A 1980-10-14 1980-10-14 Bias varying circuit Granted JPS5767331A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55143320A JPS5767331A (en) 1980-10-14 1980-10-14 Bias varying circuit
US06/295,825 US4464587A (en) 1980-10-14 1981-08-24 Complementary IGFET Schmitt trigger logic circuit having a variable bias voltage logic gate section

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55143320A JPS5767331A (en) 1980-10-14 1980-10-14 Bias varying circuit

Publications (2)

Publication Number Publication Date
JPS5767331A true JPS5767331A (en) 1982-04-23
JPH0133974B2 JPH0133974B2 (en) 1989-07-17

Family

ID=15336033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55143320A Granted JPS5767331A (en) 1980-10-14 1980-10-14 Bias varying circuit

Country Status (1)

Country Link
JP (1) JPS5767331A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943631A (en) * 1982-09-06 1984-03-10 Hitachi Ltd Level converting input circuit
JPS59171216A (en) * 1983-03-17 1984-09-27 Nec Corp Input sampling pulse generating circuit of charge transfer element
JPS61244115A (en) * 1985-04-22 1986-10-30 Nec Corp Current-controlled oscillator
US6127898A (en) * 1997-01-13 2000-10-03 Sgs-Thomson Microelectroncs S.A. Ring oscillator using CMOS technology
WO2020225893A1 (en) * 2019-05-08 2020-11-12 日本電信電話株式会社 Transimpedance amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315056A (en) * 1976-07-27 1978-02-10 Toshiba Corp Logic circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315056A (en) * 1976-07-27 1978-02-10 Toshiba Corp Logic circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943631A (en) * 1982-09-06 1984-03-10 Hitachi Ltd Level converting input circuit
JPH0422050B2 (en) * 1982-09-06 1992-04-15 Hitachi Ltd
JPS59171216A (en) * 1983-03-17 1984-09-27 Nec Corp Input sampling pulse generating circuit of charge transfer element
JPS61244115A (en) * 1985-04-22 1986-10-30 Nec Corp Current-controlled oscillator
JPH0423963B2 (en) * 1985-04-22 1992-04-23 Nippon Electric Co
US6127898A (en) * 1997-01-13 2000-10-03 Sgs-Thomson Microelectroncs S.A. Ring oscillator using CMOS technology
WO2020225893A1 (en) * 2019-05-08 2020-11-12 日本電信電話株式会社 Transimpedance amplifier
JPWO2020225893A1 (en) * 2019-05-08 2020-11-12

Also Published As

Publication number Publication date
JPH0133974B2 (en) 1989-07-17

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