JPS5767324A - Constitution system for floating-point analogue-digital converter - Google Patents
Constitution system for floating-point analogue-digital converterInfo
- Publication number
- JPS5767324A JPS5767324A JP14408880A JP14408880A JPS5767324A JP S5767324 A JPS5767324 A JP S5767324A JP 14408880 A JP14408880 A JP 14408880A JP 14408880 A JP14408880 A JP 14408880A JP S5767324 A JPS5767324 A JP S5767324A
- Authority
- JP
- Japan
- Prior art keywords
- converter
- output
- floating
- digital converter
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To realize a floating-point A/D conversion function without a gain switch in the analogue stage, by selecting another A/D converter by discriminating whether an input is within a normal operation range of not. CONSTITUTION:A momentary level is detected by a level detector 6; an if it is within a normal operation range of an A/D converter 4, the output of the A/D con- verter 4 is selected by a digital signal synthesizer 7. If it exceeds the level range of the A/D converter 4, the output of an A/D converter 3 is selected by the digital signal synthesizer 7. The expontential part is set to zero if the output of the A/D converter 4 is selected, and a proper value of 0 or 1 is substituted in the lower bit of the mantissa, if the output of the A/D converter 3 is selected, thereby obtaining a floating point indication.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14408880A JPS5767324A (en) | 1980-10-14 | 1980-10-14 | Constitution system for floating-point analogue-digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14408880A JPS5767324A (en) | 1980-10-14 | 1980-10-14 | Constitution system for floating-point analogue-digital converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5767324A true JPS5767324A (en) | 1982-04-23 |
Family
ID=15353945
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14408880A Pending JPS5767324A (en) | 1980-10-14 | 1980-10-14 | Constitution system for floating-point analogue-digital converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5767324A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62178017A (en) * | 1986-01-31 | 1987-08-05 | Sony Corp | Gain control circuit |
JPS6370618A (en) * | 1986-09-11 | 1988-03-30 | Shimadzu Corp | Analog-digital converter |
JPS63174429A (en) * | 1987-01-13 | 1988-07-18 | Nec Corp | Floating point type analog/digital converter |
-
1980
- 1980-10-14 JP JP14408880A patent/JPS5767324A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62178017A (en) * | 1986-01-31 | 1987-08-05 | Sony Corp | Gain control circuit |
JPS6370618A (en) * | 1986-09-11 | 1988-03-30 | Shimadzu Corp | Analog-digital converter |
JPS63174429A (en) * | 1987-01-13 | 1988-07-18 | Nec Corp | Floating point type analog/digital converter |
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