JPS5764846A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPS5764846A
JPS5764846A JP13948880A JP13948880A JPS5764846A JP S5764846 A JPS5764846 A JP S5764846A JP 13948880 A JP13948880 A JP 13948880A JP 13948880 A JP13948880 A JP 13948880A JP S5764846 A JPS5764846 A JP S5764846A
Authority
JP
Japan
Prior art keywords
instruction code
user
decoder
instruction
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13948880A
Other languages
Japanese (ja)
Inventor
Hiromi Nagayoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13948880A priority Critical patent/JPS5764846A/en
Publication of JPS5764846A publication Critical patent/JPS5764846A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To ensure the optional decision of a machine word instruction code, by constituting an instruction decoder with a memory device the user can optionally rewrites. CONSTITUTION:An instruction decoder 11 of a microprocessor is constituted with a memory device such as an EPROM the user can freely rewrites. The user can store a machine word instruction code the or she previously intends via a data bus 13 which is used to supply the control signal which is applied from a control input 14 to write an instruction code into the decoder 11, an address input given from an address buffer 15 to designate the position of the instruction code to be written plus the instruction code respectively.
JP13948880A 1980-10-03 1980-10-03 Microprocessor Pending JPS5764846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13948880A JPS5764846A (en) 1980-10-03 1980-10-03 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13948880A JPS5764846A (en) 1980-10-03 1980-10-03 Microprocessor

Publications (1)

Publication Number Publication Date
JPS5764846A true JPS5764846A (en) 1982-04-20

Family

ID=15246417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13948880A Pending JPS5764846A (en) 1980-10-03 1980-10-03 Microprocessor

Country Status (1)

Country Link
JP (1) JPS5764846A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62231337A (en) * 1986-03-31 1987-10-09 Toshiba Corp Microprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62231337A (en) * 1986-03-31 1987-10-09 Toshiba Corp Microprocessor

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