JPS5760845A - Manufacture of hybrid ic - Google Patents

Manufacture of hybrid ic

Info

Publication number
JPS5760845A
JPS5760845A JP13559380A JP13559380A JPS5760845A JP S5760845 A JPS5760845 A JP S5760845A JP 13559380 A JP13559380 A JP 13559380A JP 13559380 A JP13559380 A JP 13559380A JP S5760845 A JPS5760845 A JP S5760845A
Authority
JP
Japan
Prior art keywords
lead
exterior
lead frames
resin
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13559380A
Other languages
Japanese (ja)
Inventor
Ryoichi Ozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13559380A priority Critical patent/JPS5760845A/en
Publication of JPS5760845A publication Critical patent/JPS5760845A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405—Edge mounted components, e.g. terminals

Abstract

PURPOSE:To facilitate exterior formation and assembly, and reduce manufacturing cost, by cutting off and terminating lead frames, after holding and mounting an IC board with a lead of lead frames, and coating the whole surface thereof with exterior resin by means of fluid dipping. CONSTITUTION:In a manufacturing process of a resin-sealed DIP bybrid IC, clamps 4 are attached to the junctions of leads 3, 3' of lead frames. Terminals of a board 2 are engaged to make a rough assembly 10. Next, the assembly 10 is coated on the whole surface including the lead frames with exterior resin 6 made of epoxy resin flour by means of fluid dipping. Next, a frame 5 is cut off at line 8 position. The lead 3 is bent perpendicularly at line 7 position. The resin applied on the lead 3 is removed to complete the assembly. This arranges the board and the lead frames level, facilitates exterior formation, and reduces the cost of equipment and exterior.
JP13559380A 1980-09-29 1980-09-29 Manufacture of hybrid ic Pending JPS5760845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13559380A JPS5760845A (en) 1980-09-29 1980-09-29 Manufacture of hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13559380A JPS5760845A (en) 1980-09-29 1980-09-29 Manufacture of hybrid ic

Publications (1)

Publication Number Publication Date
JPS5760845A true JPS5760845A (en) 1982-04-13

Family

ID=15155441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13559380A Pending JPS5760845A (en) 1980-09-29 1980-09-29 Manufacture of hybrid ic

Country Status (1)

Country Link
JP (1) JPS5760845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816427A (en) * 1986-09-02 1989-03-28 Dennis Richard K Process for connecting lead frame to semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816427A (en) * 1986-09-02 1989-03-28 Dennis Richard K Process for connecting lead frame to semiconductor device

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