JPS5755439A - Common bus control system - Google Patents

Abstract

PURPOSE:To realize the sure management with a simple circuit, by starting or stopping of exclusive use of buses by a managing device, through the presence of a transfer request signal from a plurality of input and output controllers connected to a common bus. CONSTITUTION:A data transfer request condition 31 produced between input and output devices managed with a main storage device 2 and input and output controller 3-1' which are connected to a common bus 4, a filp-flop (FF)32 is set, and a transfer request signal 41 is transmitted to an FF1 of a central processing unit 1' via a common bus 4. The FF11 is set, and the occupying right of the common bus 4 is given to the input and output controller 3-1'. When the transfer is finished, a signal 42 from the storage device 42 is outputted, and an FF32 is reset with a signal 45 via a gate 37. When a transfer request signal 41 is transmitted to a time limit circuit 33 and a specified time is elapsed, a time limit signal 43 is outputted and the FF32 is reset via the gate 37. Thus, the transfer request signal 41 vanishes, and an inverter 12 resets the FF11. Thus, the buses are controlled surely with a simple device.