JPS5755438A - Data processing unit - Google Patents
Data processing unitInfo
- Publication number
- JPS5755438A JPS5755438A JP55129331A JP12933180A JPS5755438A JP S5755438 A JPS5755438 A JP S5755438A JP 55129331 A JP55129331 A JP 55129331A JP 12933180 A JP12933180 A JP 12933180A JP S5755438 A JPS5755438 A JP S5755438A
- Authority
- JP
- Japan
- Prior art keywords
- giving
- bus
- operation processing
- input
- processing units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To prevent the device from complication, by performing data processing singly, making common the input and output buses of a plurality of operation processing units receiving and giving data mutually, and giving a specified phase difference to the operation timing. CONSTITUTION:An output bus Z, and input buses X, Y of a plurality of, e.g., 2 sets of, arithmetic operation processing units A, B, which make data processing singly and data reception/giving mutually, are made common. Each arithmetic operation processing unit consists of an operating circuit ALUA (B), exclusive register RA (B), communication register IFRA (B) and a selector. Taking notice that the bus is actually used at the first half of the machine cycle at the input bus and at the latter half, the output bus, AND gate 114, 117, 118 and 124, 127, 128 are provided, and the gates are allowed to open only when timing signals TXA-TZA, TXB-TZB are inputted, the operation of the arithmetic operation processing units as the time chart shown in Figure is controlled. Thus, complication of devices around the communication registers are avoided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55129331A JPS5755438A (en) | 1980-09-19 | 1980-09-19 | Data processing unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55129331A JPS5755438A (en) | 1980-09-19 | 1980-09-19 | Data processing unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5755438A true JPS5755438A (en) | 1982-04-02 |
Family
ID=15006952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55129331A Pending JPS5755438A (en) | 1980-09-19 | 1980-09-19 | Data processing unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5755438A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58164046U (en) * | 1982-04-21 | 1983-11-01 | アルプス電気株式会社 | Microprocessor control device |
| JPH0267986U (en) * | 1988-11-11 | 1990-05-23 |
-
1980
- 1980-09-19 JP JP55129331A patent/JPS5755438A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58164046U (en) * | 1982-04-21 | 1983-11-01 | アルプス電気株式会社 | Microprocessor control device |
| JPH0267986U (en) * | 1988-11-11 | 1990-05-23 |
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