JPS5750397A - Memory circuit capable of production of error correction code and correction of error - Google Patents
Memory circuit capable of production of error correction code and correction of errorInfo
- Publication number
- JPS5750397A JPS5750397A JP55124876A JP12487680A JPS5750397A JP S5750397 A JPS5750397 A JP S5750397A JP 55124876 A JP55124876 A JP 55124876A JP 12487680 A JP12487680 A JP 12487680A JP S5750397 A JPS5750397 A JP S5750397A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- stage
- error
- constitution
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE:To simplify the constitution of a memory circuit without using a parity producing matrix, by reading out the check bits along with the information bits out of a memory and then delivering these bits directly or after a correction if necessary. CONSTITUTION:Information bits RD0-RD7 read out from a memory array which is reversed by an externally written data WD in the writing mode are designated through gate circuits 4- of the first stage to logical integral circuits 2- of the fourth stage having a 6-stage circuit constitution of a circuit which is capable of producing an error correction code and correcting errors. Then check bits RC0- RC3 read out from the memory array along withthe bits RD0-RD7 receive a reverse correction in accordance with the data WD and through exclusive OR circuits 1'- of the fifth stage. Furthermore, if a 1'-bit error exists in the bits RC0- RC3, the check bit is delivered through exclusive OR circuits 1- of the sixth stage after reversed according to syndromes S0-S3 and with no use of a parity producing matrix. Thus the constitution can be simplified for a circuit which is capable of producing an error correction code and correcting errors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55124876A JPS5750397A (en) | 1980-09-09 | 1980-09-09 | Memory circuit capable of production of error correction code and correction of error |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55124876A JPS5750397A (en) | 1980-09-09 | 1980-09-09 | Memory circuit capable of production of error correction code and correction of error |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5750397A true JPS5750397A (en) | 1982-03-24 |
JPS6232823B2 JPS6232823B2 (en) | 1987-07-16 |
Family
ID=14896275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55124876A Granted JPS5750397A (en) | 1980-09-09 | 1980-09-09 | Memory circuit capable of production of error correction code and correction of error |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5750397A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6458197A (en) * | 1987-08-28 | 1989-03-06 | Nippon Telegraph & Telephone | Method for constituting line setting section |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5298434A (en) * | 1976-02-14 | 1977-08-18 | Hitachi Ltd | Correction for memory error |
-
1980
- 1980-09-09 JP JP55124876A patent/JPS5750397A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5298434A (en) * | 1976-02-14 | 1977-08-18 | Hitachi Ltd | Correction for memory error |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6458197A (en) * | 1987-08-28 | 1989-03-06 | Nippon Telegraph & Telephone | Method for constituting line setting section |
Also Published As
Publication number | Publication date |
---|---|
JPS6232823B2 (en) | 1987-07-16 |
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