JPS5746388A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS5746388A JPS5746388A JP55121887A JP12188780A JPS5746388A JP S5746388 A JPS5746388 A JP S5746388A JP 55121887 A JP55121887 A JP 55121887A JP 12188780 A JP12188780 A JP 12188780A JP S5746388 A JPS5746388 A JP S5746388A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- drain
- memory device
- semiconductor memory
- trq42
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To realize a high-speed operation of a semiconductor memory device without lowering the S/N, by carrying out the refresh action, the writing and reading actions in the independent timing respectively. CONSTITUTION:The source of a MOS transistor (TR) Q22 is connected to the reference potential (the earth potential in this example), and a drain is connected the data line BL via a TRQ12 that constitutes a transfer gate. The source and the gate of a TRQ42 are connected to the gate of the TRQ22 and the drain of a TRQ32 with the drain connected to a refresh terminal R in common with a memory cell. A capacity C is connected between the gate of the TRQ42 and the terminal R. Furthermore a word line WL is connected to the gate of the TRQ12, and the drain of the TRQ22 is connected to a power source VCC via a load resistance RL.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55121887A JPS5746388A (en) | 1980-09-03 | 1980-09-03 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55121887A JPS5746388A (en) | 1980-09-03 | 1980-09-03 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5746388A true JPS5746388A (en) | 1982-03-16 |
Family
ID=14822363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55121887A Pending JPS5746388A (en) | 1980-09-03 | 1980-09-03 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5746388A (en) |
-
1980
- 1980-09-03 JP JP55121887A patent/JPS5746388A/en active Pending
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