JPS5746308A - Digital recording and reproducing system - Google Patents
Digital recording and reproducing systemInfo
- Publication number
- JPS5746308A JPS5746308A JP12300380A JP12300380A JPS5746308A JP S5746308 A JPS5746308 A JP S5746308A JP 12300380 A JP12300380 A JP 12300380A JP 12300380 A JP12300380 A JP 12300380A JP S5746308 A JPS5746308 A JP S5746308A
- Authority
- JP
- Japan
- Prior art keywords
- error
- parities
- delays
- receive
- carried out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To increase the error correcting efficiency, by carrying out the detection and correction of error only to the data having a genuine error. CONSTITUTION:The original information signals are divided into two parts via a switch 11 and stored in buffer registers 12a snd 12b in the form of data trains X and Y respectively. The train Y is delivered via a delaying circuit 13, and then an interleaving operation of D is carried out for trains X and Y. The parities P1 and Q1 poduced by the 1st parity adding circuts 14a and 14b receive 2D and 3D delays 15a and 15b and then (d-D), 2(d-D) and 3(d-D) delays 16a, 16b and 16c to receive an interleaving control. These actions are repeated, and the information signal is recorded via a multiplexer 23. For reproduction of this information signal, the error correction is carried out for the parities in the order of P3, Q3, P2, Q2, P1 and Q1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12300380A JPS5746308A (en) | 1980-09-05 | 1980-09-05 | Digital recording and reproducing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12300380A JPS5746308A (en) | 1980-09-05 | 1980-09-05 | Digital recording and reproducing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5746308A true JPS5746308A (en) | 1982-03-16 |
Family
ID=14849847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12300380A Pending JPS5746308A (en) | 1980-09-05 | 1980-09-05 | Digital recording and reproducing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5746308A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60201576A (en) * | 1984-03-24 | 1985-10-12 | Sony Corp | Digital data transmission method |
-
1980
- 1980-09-05 JP JP12300380A patent/JPS5746308A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60201576A (en) * | 1984-03-24 | 1985-10-12 | Sony Corp | Digital data transmission method |
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