JPS5740981A - Ultra-high speed semiconductor device - Google Patents

Ultra-high speed semiconductor device

Info

Publication number
JPS5740981A
JPS5740981A JP11598080A JP11598080A JPS5740981A JP S5740981 A JPS5740981 A JP S5740981A JP 11598080 A JP11598080 A JP 11598080A JP 11598080 A JP11598080 A JP 11598080A JP S5740981 A JPS5740981 A JP S5740981A
Authority
JP
Japan
Prior art keywords
insb
layer
mobility
impurity concentration
hetero junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11598080A
Other languages
Japanese (ja)
Inventor
Takashi Andou
Masashi Yamaguchi
Akio Yamamoto
Zeio Kamimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11598080A priority Critical patent/JPS5740981A/en
Publication of JPS5740981A publication Critical patent/JPS5740981A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain an FET capable of high-speed operation at low temperature, by a method wherein a high-mobility single crystal, such as InSb, InAs, CdSnAs2 or the like, provided on a semiinsulator substrate is used as an operating layer, and a hetero junction type gate structure is formed. CONSTITUTION:On a semiinsulator InSb substrate (single crystal) 7, an epitaxial film 8 of InSb having a low impurity concentration and a high mobility is formed, and thereon, a CdTe monocrystalline thin film 9 of high impurity concentration is epitaxially grown to form a hetero junction, and the high-mobility InSb layer directly below said layer is defined as an operating layer 10. Thus, the current flowing between a source 11 and a drain 12 can be controlled by means of the bias voltage applied to an Au gate electrode 13. As a result, the channel is realized by means of the InSb layer of high mobility, and owing to the hetero junction type gate structure, the InSb layer having a low impurity concentration and a high mibility can be utilized.
JP11598080A 1980-08-25 1980-08-25 Ultra-high speed semiconductor device Pending JPS5740981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11598080A JPS5740981A (en) 1980-08-25 1980-08-25 Ultra-high speed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11598080A JPS5740981A (en) 1980-08-25 1980-08-25 Ultra-high speed semiconductor device

Publications (1)

Publication Number Publication Date
JPS5740981A true JPS5740981A (en) 1982-03-06

Family

ID=14675889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11598080A Pending JPS5740981A (en) 1980-08-25 1980-08-25 Ultra-high speed semiconductor device

Country Status (1)

Country Link
JP (1) JPS5740981A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963768A (en) * 1982-10-05 1984-04-11 Agency Of Ind Science & Technol Field-effect type semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577165A (en) * 1980-06-17 1982-01-14 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577165A (en) * 1980-06-17 1982-01-14 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963768A (en) * 1982-10-05 1984-04-11 Agency Of Ind Science & Technol Field-effect type semiconductor device

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