JPS5740794A - Address inverter circuit - Google Patents

Address inverter circuit

Info

Publication number
JPS5740794A
JPS5740794A JP55115180A JP11518080A JPS5740794A JP S5740794 A JPS5740794 A JP S5740794A JP 55115180 A JP55115180 A JP 55115180A JP 11518080 A JP11518080 A JP 11518080A JP S5740794 A JPS5740794 A JP S5740794A
Authority
JP
Japan
Prior art keywords
trs
output
address inverter
turn
decreased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55115180A
Other languages
Japanese (ja)
Other versions
JPS614131B2 (en
Inventor
Tetsuo Misaizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55115180A priority Critical patent/JPS5740794A/en
Publication of JPS5740794A publication Critical patent/JPS5740794A/en
Publication of JPS614131B2 publication Critical patent/JPS614131B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To improve rising-falling characteristics by adding a reset circuit to the output of an address inverter buffer circuit. CONSTITUTION:The output of an address inverter buffer held at the high potential of a power source Vcc in the last cycle, when becoming unselected, is placed in a floating state because nodes 4 and 6 go down to low potentials. At this time, transistors (TR) Q16 and Q17 applied with a one-shot type pulse turn on to decrease the high-potential levle in the floaing state. The TRs Q16 and Q17 have small performance than TRs Q10 and Q12 have, so the decreased level nearly equals a level increased by the threshold levels of depletion type MOSTRs Q10 and Q12. Because of the one-shot pulse, the output is decreased and then the TRs Q16 and Q17 turn off.
JP55115180A 1980-08-21 1980-08-21 Address inverter circuit Granted JPS5740794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55115180A JPS5740794A (en) 1980-08-21 1980-08-21 Address inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55115180A JPS5740794A (en) 1980-08-21 1980-08-21 Address inverter circuit

Publications (2)

Publication Number Publication Date
JPS5740794A true JPS5740794A (en) 1982-03-06
JPS614131B2 JPS614131B2 (en) 1986-02-07

Family

ID=14656325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55115180A Granted JPS5740794A (en) 1980-08-21 1980-08-21 Address inverter circuit

Country Status (1)

Country Link
JP (1) JPS5740794A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504746A (en) * 1981-04-16 1985-03-12 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor buffer circuit using enhancement-mode, depletion-mode and zero threshold mode transistors
JPS62292015A (en) * 1986-06-11 1987-12-18 Nec Corp Output buffer circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504746A (en) * 1981-04-16 1985-03-12 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor buffer circuit using enhancement-mode, depletion-mode and zero threshold mode transistors
JPS62292015A (en) * 1986-06-11 1987-12-18 Nec Corp Output buffer circuit

Also Published As

Publication number Publication date
JPS614131B2 (en) 1986-02-07

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