JPS5739649A - Communication speed reducing system - Google Patents

Communication speed reducing system

Info

Publication number
JPS5739649A
JPS5739649A JP55114846A JP11484680A JPS5739649A JP S5739649 A JPS5739649 A JP S5739649A JP 55114846 A JP55114846 A JP 55114846A JP 11484680 A JP11484680 A JP 11484680A JP S5739649 A JPS5739649 A JP S5739649A
Authority
JP
Japan
Prior art keywords
speed
communication
data
terminals
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55114846A
Other languages
Japanese (ja)
Inventor
Tadashi Yatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55114846A priority Critical patent/JPS5739649A/en
Publication of JPS5739649A publication Critical patent/JPS5739649A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To enable the connection of a plurality of terminal devices in different speeds by reducing the communication speed without changing barrier rate, through the provision of a means which reduces an apparent communication speed, in a digital data network. CONSTITUTION:Terminal devices 1 and 4 coupled with lines in a specified speed via a data communication network include respectively subterminals A, B and C, D. The terminals A, C are data transmitter/receiver having the above line speed and the terminals B, D are data transmitter/receiver having slower speed. In the communication with slower line speed from the communication between the terminals A and C, a line terminator 2 makes the signal bit of the envelope signal in the specified rate to 1 and the signal transmitted from the terminal B is inserted to the succeeding data bit. In other envelope signals, the signal bit is taken as 0 and all the data bits are made to 1.
JP55114846A 1980-08-22 1980-08-22 Communication speed reducing system Pending JPS5739649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55114846A JPS5739649A (en) 1980-08-22 1980-08-22 Communication speed reducing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55114846A JPS5739649A (en) 1980-08-22 1980-08-22 Communication speed reducing system

Publications (1)

Publication Number Publication Date
JPS5739649A true JPS5739649A (en) 1982-03-04

Family

ID=14648165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55114846A Pending JPS5739649A (en) 1980-08-22 1980-08-22 Communication speed reducing system

Country Status (1)

Country Link
JP (1) JPS5739649A (en)

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