JPS5735327A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5735327A JPS5735327A JP11019780A JP11019780A JPS5735327A JP S5735327 A JPS5735327 A JP S5735327A JP 11019780 A JP11019780 A JP 11019780A JP 11019780 A JP11019780 A JP 11019780A JP S5735327 A JPS5735327 A JP S5735327A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nitrogen content
- content
- silicon
- refractive index
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a passivation film excellent in electrical characteristics, contamination-resisting performance and crack-preventing performance, by increasing the nitrogen content on outside of a silicon nitride film covering the surface of a semiconductor, and also by increasing the silicon-content on the semiconductor side. CONSTITUTION:P type resistance regions 2 and 3 are formed on an N type epitaxial layer 1 by diffusion, and an SiO2 film 4 and a silicate phosphorus glass film 7 are provided to cover a surface containing these regions. Further, a P-SiN film 15 is allowed to grow on this. The top layer 15a of the P-SiN film 15 is a film of a relatively high nitrogen content and a low refractive index, and a bottom layer 15b is a film of a relatively high nitrogen content and a high refractive index. It is possible, by providing a film of a high nitrogen content, to lower conductivity, prevent injection of charge through the film and occurrence of polarization phenomenon, and increase strength. By providing the film of a high silicon content, it is possible to prevent the film from coming off.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11019780A JPS5735327A (en) | 1980-08-13 | 1980-08-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11019780A JPS5735327A (en) | 1980-08-13 | 1980-08-13 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5735327A true JPS5735327A (en) | 1982-02-25 |
JPS6322059B2 JPS6322059B2 (en) | 1988-05-10 |
Family
ID=14529502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11019780A Granted JPS5735327A (en) | 1980-08-13 | 1980-08-13 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5735327A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60216554A (en) * | 1984-04-12 | 1985-10-30 | Fuji Electric Corp Res & Dev Ltd | Photoetching method |
JPS6439030A (en) * | 1987-08-05 | 1989-02-09 | Toshiba Corp | Formation of thin film |
EP0601093A1 (en) * | 1991-08-28 | 1994-06-15 | Advanced Power Technology Inc. | Igbt process and device with platinum lifetime control |
JP2012182232A (en) * | 2011-02-28 | 2012-09-20 | Sumitomo Electric Device Innovations Inc | Method of manufacturing semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS554918A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Passivation film structure and manufacturing method thereof |
-
1980
- 1980-08-13 JP JP11019780A patent/JPS5735327A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS554918A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Passivation film structure and manufacturing method thereof |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60216554A (en) * | 1984-04-12 | 1985-10-30 | Fuji Electric Corp Res & Dev Ltd | Photoetching method |
JPS6439030A (en) * | 1987-08-05 | 1989-02-09 | Toshiba Corp | Formation of thin film |
EP0601093A1 (en) * | 1991-08-28 | 1994-06-15 | Advanced Power Technology Inc. | Igbt process and device with platinum lifetime control |
EP0601093A4 (en) * | 1991-08-28 | 1995-04-12 | Advanced Power Technology | Igbt process and device with platinum lifetime control. |
EP1182706A2 (en) * | 1991-08-28 | 2002-02-27 | Advanced Power Technology Inc. | IGBT process and device |
EP1182706A3 (en) * | 1991-08-28 | 2003-10-08 | Advanced Power Technology Inc. | IGBT process and device |
JP2012182232A (en) * | 2011-02-28 | 2012-09-20 | Sumitomo Electric Device Innovations Inc | Method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6322059B2 (en) | 1988-05-10 |
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