JPS5728335A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5728335A
JPS5728335A JP10247980A JP10247980A JPS5728335A JP S5728335 A JPS5728335 A JP S5728335A JP 10247980 A JP10247980 A JP 10247980A JP 10247980 A JP10247980 A JP 10247980A JP S5728335 A JPS5728335 A JP S5728335A
Authority
JP
Japan
Prior art keywords
psg
thickness
si3n4
film
xtp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10247980A
Other languages
Japanese (ja)
Inventor
Yuji Hara
Tatsuro Totani
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP10247980A priority Critical patent/JPS5728335A/en
Publication of JPS5728335A publication Critical patent/JPS5728335A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain necessary and enough strength of a device and improve its endurance against humidity by putting on an element circuit PSG and Si3N4 in order with thickness of each film being specified. CONSTITUTION:PSG16 (tP in thickness) and Si3N417 (tN in thickness) are laid on an element circuit formed with an SiO2 film 13 and an Al wiring 15 on an Si substrate 10. By said constituion, the PSG will restrain Na<+> ions and so on in SiO2 from wafting with P for stabilizing element property, and Si3N4 will repel water invading from the outside with its minuteness for protecting PSG which is easily affected by water. Further, if the thickness of a film is settled to be within a scope tN+ (1/k)XtP>=1mum(1.5<=k<=2.5), internal strength will improve as well as the endurance against humidity, preventing cracks on PSG and Si3N4 therefore increasing manufacturing efficiency of a device and decreasing cost for it. It is also effective if PSG, amorphous Si (tA in thickness) and Si3N4 are laminated maintaining a relation of tN+tA+(1/k)XtP>=1mum.
JP10247980A 1980-07-28 1980-07-28 Semiconductor device Pending JPS5728335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10247980A JPS5728335A (en) 1980-07-28 1980-07-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10247980A JPS5728335A (en) 1980-07-28 1980-07-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5728335A true JPS5728335A (en) 1982-02-16

Family

ID=14328582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10247980A Pending JPS5728335A (en) 1980-07-28 1980-07-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5728335A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728188U (en) * 1980-07-23 1982-02-15
JPS59128218U (en) * 1983-02-18 1984-08-29 株式会社エムケイエンタプライズ Money sorting piggy bank
JPS60117633A (en) * 1983-11-30 1985-06-25 Toshiba Corp Semiconductor device
JPS60245137A (en) * 1984-05-21 1985-12-04 Toshiba Corp Semiconductor device
JPS6181630A (en) * 1984-06-28 1986-04-25 Toshiba Corp Semiconductor device and manufacture thereof
JPS62194631A (en) * 1986-02-20 1987-08-27 Mitsubishi Electric Corp Manufacture of semiconductor device
US5559052A (en) * 1994-12-29 1996-09-24 Lucent Technologies Inc. Integrated circuit fabrication with interlevel dielectric
US5583077A (en) * 1995-04-04 1996-12-10 Taiwan Semiconductor Manufacturing Company Ltd Integrated dual layer passivation process to suppress stress-induced metal voids
EP3823034A1 (en) * 2019-11-12 2021-05-19 Infineon Technologies AG High voltage semiconductor device with step topography passivation layer stack

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728188U (en) * 1980-07-23 1982-02-15
JPS59128218U (en) * 1983-02-18 1984-08-29 株式会社エムケイエンタプライズ Money sorting piggy bank
JPS60117633A (en) * 1983-11-30 1985-06-25 Toshiba Corp Semiconductor device
JPS60245137A (en) * 1984-05-21 1985-12-04 Toshiba Corp Semiconductor device
JPS6181630A (en) * 1984-06-28 1986-04-25 Toshiba Corp Semiconductor device and manufacture thereof
JPS62194631A (en) * 1986-02-20 1987-08-27 Mitsubishi Electric Corp Manufacture of semiconductor device
US5559052A (en) * 1994-12-29 1996-09-24 Lucent Technologies Inc. Integrated circuit fabrication with interlevel dielectric
US5583077A (en) * 1995-04-04 1996-12-10 Taiwan Semiconductor Manufacturing Company Ltd Integrated dual layer passivation process to suppress stress-induced metal voids
EP3823034A1 (en) * 2019-11-12 2021-05-19 Infineon Technologies AG High voltage semiconductor device with step topography passivation layer stack

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