JPS57212534A - Interface repeating system - Google Patents

Interface repeating system

Info

Publication number
JPS57212534A
JPS57212534A JP56097960A JP9796081A JPS57212534A JP S57212534 A JPS57212534 A JP S57212534A JP 56097960 A JP56097960 A JP 56097960A JP 9796081 A JP9796081 A JP 9796081A JP S57212534 A JPS57212534 A JP S57212534A
Authority
JP
Japan
Prior art keywords
sequence
signal
adaptor
synchronizing signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56097960A
Other languages
Japanese (ja)
Inventor
Hiroshi Hasegawa
Tetsuhiko Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56097960A priority Critical patent/JPS57212534A/en
Publication of JPS57212534A publication Critical patent/JPS57212534A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize conversion to a long distance between a channel device and an input/output device easily and economically, by providing an adaptor between the channel device and the input/output device so that a data, etc. can be transferred at a high speed by an optical signal between the adaptors. CONSTITUTION:Transmission frame controlling circuits SFCa, SFCb are operated, an adaptor ADP1 sends out a synchronizing signal and a state of a channel interface CH.I/F, and an adaptor ADP2 sends out a synchronizing signal and a state of an I/O CH.I/F. Receiving frame controlling circuits RFCa, RFCb detect the synchronizing signal from photoelectric converters OEa, OEb, shift the signal as a receiving data into registers R1a, R1b, set it to R2a, R2b, and also to R3a, R3b, and transfer it to CH.I/F circuits IFa, IFb. The adaptors ADP1, ADP2 relay a signal between the CH device and the I/O device. In this way, in the start sequence, in case of a command which requires a data transfer, it is shifted to the data transfer sequence after the start sequence has ended, and it becomes the end sequence after said sequence has ended.
JP56097960A 1981-06-24 1981-06-24 Interface repeating system Pending JPS57212534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56097960A JPS57212534A (en) 1981-06-24 1981-06-24 Interface repeating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56097960A JPS57212534A (en) 1981-06-24 1981-06-24 Interface repeating system

Publications (1)

Publication Number Publication Date
JPS57212534A true JPS57212534A (en) 1982-12-27

Family

ID=14206233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56097960A Pending JPS57212534A (en) 1981-06-24 1981-06-24 Interface repeating system

Country Status (1)

Country Link
JP (1) JPS57212534A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329624A (en) * 1990-12-27 1994-07-12 Nec Corporation Method of controlling data transfer between main memory of central computer and input/output device and arrangement therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329624A (en) * 1990-12-27 1994-07-12 Nec Corporation Method of controlling data transfer between main memory of central computer and input/output device and arrangement therefor

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