JPS57210662A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS57210662A
JPS57210662A JP56093812A JP9381281A JPS57210662A JP S57210662 A JPS57210662 A JP S57210662A JP 56093812 A JP56093812 A JP 56093812A JP 9381281 A JP9381281 A JP 9381281A JP S57210662 A JPS57210662 A JP S57210662A
Authority
JP
Japan
Prior art keywords
wire
polysilicon layer
wires
load
drain region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56093812A
Other languages
Japanese (ja)
Inventor
Noburo Tanimura
Yoshio Sakai
Akira Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56093812A priority Critical patent/JPS57210662A/en
Publication of JPS57210662A publication Critical patent/JPS57210662A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to contract the size of a cell by forming a load resistance part of the second polysilicon layer, thereby enabling the overlap of a gate electrode and the load resistance part. CONSTITUTION:The gate electrodes G1, G2 and their wires l2, a word line W of FETs Q1, Q2 in a static memory cell formed of MISFETs Q1-Q4 formed on an element region isolated with a field SiO2 film 3 on a P type well 2 on a substrate 1 are formed of the first polysilicon layer, and load resistors R1, R2 and their wires l'1, power line l1 are formed of second polysilicon layer. An N<+> drain region 4 is contacted directly with the wire l2 from the gate electrode G2, and the wire l2 is connected to the second layer polysilicon wire l'1 at the connecting position. In this manner, the connections of the electrode G2, the drain region 4 and the load resistor R1 can be performed at one position.
JP56093812A 1981-06-19 1981-06-19 Semiconductor memory device Pending JPS57210662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56093812A JPS57210662A (en) 1981-06-19 1981-06-19 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56093812A JPS57210662A (en) 1981-06-19 1981-06-19 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS57210662A true JPS57210662A (en) 1982-12-24

Family

ID=14092807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56093812A Pending JPS57210662A (en) 1981-06-19 1981-06-19 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS57210662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268451A (en) * 1990-03-19 1991-11-29 Nippon Precision Circuits Kk Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268451A (en) * 1990-03-19 1991-11-29 Nippon Precision Circuits Kk Semiconductor device
JPH073835B2 (en) * 1990-03-19 1995-01-18 日本プレシジョン・サーキッツ株式会社 Semiconductor device

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