JPS57206904A - Device controlling system - Google Patents
Device controlling systemInfo
- Publication number
- JPS57206904A JPS57206904A JP9196981A JP9196981A JPS57206904A JP S57206904 A JPS57206904 A JP S57206904A JP 9196981 A JP9196981 A JP 9196981A JP 9196981 A JP9196981 A JP 9196981A JP S57206904 A JPS57206904 A JP S57206904A
- Authority
- JP
- Japan
- Prior art keywords
- vtr4
- main memory
- external device
- information holding
- operation command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/07—Programme control other than numerical control, i.e. in sequence controllers or logic controllers where the programme is defined in the fixed connection of electrical elements, e.g. potentiometers, counters, transistors
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
Abstract
PURPOSE:To produce a device enabling a computer to control an external device easily and quickly by providing the device with an information holding device to output an operation command to the external device and an information holding device to display the internal status of the external device. CONSTITUTION:A controlling device is provided with the 1st information holding device outputting an operation command to an external device and the 2nd information holding device displaying the internal status of the external device and addresses of a main memory are assigned to the 1st and 2nd devices. When a central processing device CPU 1 controls a video tape recorder VTR4 for example, a location ''1'' 3b of a main memory 2 which stores the internal status of the VTR 4 is read out to check the internal status of the VTR4 and then a data with a bit pattern corresponding to a required operation is written in a location ''0'' 3a of the main memory which stores the operation command for the VTR4. Subsequently the location ''1'' 3b of the main memory 2 is read out again to check whether the operation command of the VTR4 is correctly executed or not.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9196981A JPS57206904A (en) | 1981-06-15 | 1981-06-15 | Device controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9196981A JPS57206904A (en) | 1981-06-15 | 1981-06-15 | Device controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57206904A true JPS57206904A (en) | 1982-12-18 |
Family
ID=14041361
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9196981A Pending JPS57206904A (en) | 1981-06-15 | 1981-06-15 | Device controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57206904A (en) |
-
1981
- 1981-06-15 JP JP9196981A patent/JPS57206904A/en active Pending
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