JPS5720447A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5720447A
JPS5720447A JP9541480A JP9541480A JPS5720447A JP S5720447 A JPS5720447 A JP S5720447A JP 9541480 A JP9541480 A JP 9541480A JP 9541480 A JP9541480 A JP 9541480A JP S5720447 A JPS5720447 A JP S5720447A
Authority
JP
Japan
Prior art keywords
wiring layer
wire
channel
upper layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9541480A
Other languages
Japanese (ja)
Inventor
Tsutomu Ishikawa
Noboru Onishi
Tadaaki Masumori
Nobuo Muto
Kazumitsu Matsuzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9541480A priority Critical patent/JPS5720447A/en
Publication of JPS5720447A publication Critical patent/JPS5720447A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To highly integrate a semiconductor integrated circuit device by adjacently disposing circuit blocks on a substrate, and connecting a wiring layer formed in parallel with the upper layer wire of the block wire and a wiring layer formed perpendicularly to the upper layer between the blocks, thereby eliminating the wire occupying area. CONSTITUTION:Regions Aij for forming circuit blocks Mij are adjacently formed on a substrate without forming particularly a wire forming region. The connection in the block is performed by the lowermost wiring layer W1 and a wiring layer W2 formed in parallel, for example, with X-direction on the upper layer. (W1, W2 are not shown). q pieces of wire channels CXq are formed at a predetermined interval Dx in parallel with the W2 on the same with the wiring layer S2, and a channel CYr perpendicularly crossed with the upper layer is formed. The blocks are connected by connecting the connection terminal (tij or the like) provided on the channel CXq via the wiring layer on the CXg or connecting the wiring layers QW31, W32 through the through holes P1, P2 to the wiring layer W4 on the channel CY4. The wiring channel is thus formed on the upper layer of the circuit block, and the device can be highly integrated.
JP9541480A 1980-07-11 1980-07-11 Semiconductor integrated circuit device Pending JPS5720447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9541480A JPS5720447A (en) 1980-07-11 1980-07-11 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9541480A JPS5720447A (en) 1980-07-11 1980-07-11 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5720447A true JPS5720447A (en) 1982-02-02

Family

ID=14137016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9541480A Pending JPS5720447A (en) 1980-07-11 1980-07-11 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5720447A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601844A (en) * 1983-06-20 1985-01-08 Toshiba Corp Semiconductor integrated circuit device
US4636965A (en) * 1984-05-10 1987-01-13 Rca Corporation Routing method in computer-aided-customization of universal arrays and resulting integrated circuit
US4689654A (en) * 1985-04-19 1987-08-25 Nixdorf Computer Ag Logic array chip
JPH0254576A (en) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp Gate array

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601844A (en) * 1983-06-20 1985-01-08 Toshiba Corp Semiconductor integrated circuit device
US4636965A (en) * 1984-05-10 1987-01-13 Rca Corporation Routing method in computer-aided-customization of universal arrays and resulting integrated circuit
US4689654A (en) * 1985-04-19 1987-08-25 Nixdorf Computer Ag Logic array chip
JPH0254576A (en) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp Gate array

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