JPS57193827A - Interruption controlling system - Google Patents
Interruption controlling systemInfo
- Publication number
- JPS57193827A JPS57193827A JP7795081A JP7795081A JPS57193827A JP S57193827 A JPS57193827 A JP S57193827A JP 7795081 A JP7795081 A JP 7795081A JP 7795081 A JP7795081 A JP 7795081A JP S57193827 A JPS57193827 A JP S57193827A
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- channel processing
- interruption
- processing unit
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To make high speed and efficient interruption possible, by providing a storage device to which a channel processing device and a central processing unit are freely accessable. CONSTITUTION:A channel processing device operated with an instruction of a central processing unit 2 stores status information to an area assigned at each channel processing device on a storage device 4 after the end of operation and gives an interruption request signal to the central processing unit. When the central processing unit 2 can process the interruption from the channel processing device, the status information of the channel processing device is moved from the area of the storage device 4 corresponding to the channel processing device to a fixed address of a main storage device 1, and allots an interruption reception signal to the corresponding channel processing device. The corresponding channel processing device cancels the interruption request signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7795081A JPS57193827A (en) | 1981-05-25 | 1981-05-25 | Interruption controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7795081A JPS57193827A (en) | 1981-05-25 | 1981-05-25 | Interruption controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57193827A true JPS57193827A (en) | 1982-11-29 |
Family
ID=13648295
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7795081A Pending JPS57193827A (en) | 1981-05-25 | 1981-05-25 | Interruption controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57193827A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59123031A (en) * | 1982-12-29 | 1984-07-16 | Fujitsu Ltd | Control system of interruption |
-
1981
- 1981-05-25 JP JP7795081A patent/JPS57193827A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59123031A (en) * | 1982-12-29 | 1984-07-16 | Fujitsu Ltd | Control system of interruption |
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