JPS57186293A - Semiconductor storing unit - Google Patents

Semiconductor storing unit

Info

Publication number
JPS57186293A
JPS57186293A JP7104481A JP7104481A JPS57186293A JP S57186293 A JPS57186293 A JP S57186293A JP 7104481 A JP7104481 A JP 7104481A JP 7104481 A JP7104481 A JP 7104481A JP S57186293 A JPS57186293 A JP S57186293A
Authority
JP
Japan
Prior art keywords
bit lines
gate
bit
eprom
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7104481A
Other languages
Japanese (ja)
Inventor
Masanobu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7104481A priority Critical patent/JPS57186293A/en
Publication of JPS57186293A publication Critical patent/JPS57186293A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To contrive speed-up of an EPROM by reducing the parasitic capacitance, by installing an NOR gate transistor between the memory cell and the power source. CONSTITUTION:Bit lines 131-13n are connected to power sources, respectively, through bit drivers Q1-Qn which are turned on and off in accordance with the output of outputs C1-Cn of column decoders, and an NOR gate having plural transistors Tr1-Trn which receive electric potentials at connecting points N1 -Nn of the bit drivers Q1-Qn and bit lines B1-Bn at their gate and forming a pre-sensing amplifier is provided. When this circuit configuration is used, electric potentials at bit lines which change depending upon the information stored in the memory cell, enter into the pre-sensing amplifier through T1, N1, Tr1, etc., and the parasitic capacitance becomes smaller than that of conventional circuit configurations. Therefore, speed-up of the EPROM can be realized.
JP7104481A 1981-05-12 1981-05-12 Semiconductor storing unit Pending JPS57186293A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7104481A JPS57186293A (en) 1981-05-12 1981-05-12 Semiconductor storing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7104481A JPS57186293A (en) 1981-05-12 1981-05-12 Semiconductor storing unit

Publications (1)

Publication Number Publication Date
JPS57186293A true JPS57186293A (en) 1982-11-16

Family

ID=13449122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7104481A Pending JPS57186293A (en) 1981-05-12 1981-05-12 Semiconductor storing unit

Country Status (1)

Country Link
JP (1) JPS57186293A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186199A (en) * 1983-04-08 1984-10-22 Seiko Epson Corp Semiconductor memory
JPS6028098A (en) * 1983-07-25 1985-02-13 Hitachi Ltd Memory reading circuit
JPS6151696A (en) * 1984-08-22 1986-03-14 Hitachi Micro Comput Eng Ltd Semiconductor memory
JPS61187198A (en) * 1985-02-13 1986-08-20 Mitsubishi Electric Corp Semiconductor memory device
JPH01204294A (en) * 1988-02-08 1989-08-16 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH01279498A (en) * 1988-05-02 1989-11-09 Hitachi Ltd Semiconductor memory
US6418062B1 (en) * 2001-03-01 2002-07-09 Halo Lsi, Inc. Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory
US6442068B1 (en) * 1999-07-30 2002-08-27 Stmicroelectronics S.R.L. Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration
US6459621B1 (en) * 1996-09-30 2002-10-01 Hitachi, Ltd. Semiconductor integrated circuit and data processing system
JP2011165280A (en) * 2010-02-12 2011-08-25 Renesas Electronics Corp Nonvolatile semiconductor memory

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59186199A (en) * 1983-04-08 1984-10-22 Seiko Epson Corp Semiconductor memory
JPS6028098A (en) * 1983-07-25 1985-02-13 Hitachi Ltd Memory reading circuit
JPS6151696A (en) * 1984-08-22 1986-03-14 Hitachi Micro Comput Eng Ltd Semiconductor memory
JPH0522999B2 (en) * 1984-08-22 1993-03-31 Hitachi Maikon Shisutemu Kk
JPS61187198A (en) * 1985-02-13 1986-08-20 Mitsubishi Electric Corp Semiconductor memory device
JPH01204294A (en) * 1988-02-08 1989-08-16 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH01279498A (en) * 1988-05-02 1989-11-09 Hitachi Ltd Semiconductor memory
US6459621B1 (en) * 1996-09-30 2002-10-01 Hitachi, Ltd. Semiconductor integrated circuit and data processing system
US6442068B1 (en) * 1999-07-30 2002-08-27 Stmicroelectronics S.R.L. Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration
US6418062B1 (en) * 2001-03-01 2002-07-09 Halo Lsi, Inc. Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory
JP2011165280A (en) * 2010-02-12 2011-08-25 Renesas Electronics Corp Nonvolatile semiconductor memory

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