JPS5718069A - Information storage device - Google Patents

Information storage device

Info

Publication number
JPS5718069A
JPS5718069A JP9242880A JP9242880A JPS5718069A JP S5718069 A JPS5718069 A JP S5718069A JP 9242880 A JP9242880 A JP 9242880A JP 9242880 A JP9242880 A JP 9242880A JP S5718069 A JPS5718069 A JP S5718069A
Authority
JP
Japan
Prior art keywords
address
register
circuit
output data
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9242880A
Other languages
Japanese (ja)
Inventor
Isato Kazama
Kenji Baba
Hiroshi Miyajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9242880A priority Critical patent/JPS5718069A/en
Publication of JPS5718069A publication Critical patent/JPS5718069A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To decrease an average readout time, by providing an increment circuit and a specified control circuit which advance the address of an address register by ''1''. CONSTITUTION:The device is provided with an increment circuit 8 which advances the address of an address register 2 by ''1'', and a control circuit 11 which stops the operation of the circuit 8 through a storage device selection signal MS and outputs data to the outside from an output data register 6. For example, the data of a consecutive address is read out from a memory cell group 4 to the output data register 6 in advance, so that the content of the register 6 is transmitted to an external output data line 7 at the same time when an address continuous signal SEQ is given to an SEQ terminal 10.
JP9242880A 1980-07-04 1980-07-04 Information storage device Pending JPS5718069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9242880A JPS5718069A (en) 1980-07-04 1980-07-04 Information storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9242880A JPS5718069A (en) 1980-07-04 1980-07-04 Information storage device

Publications (1)

Publication Number Publication Date
JPS5718069A true JPS5718069A (en) 1982-01-29

Family

ID=14054160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9242880A Pending JPS5718069A (en) 1980-07-04 1980-07-04 Information storage device

Country Status (1)

Country Link
JP (1) JPS5718069A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0147268A2 (en) * 1983-11-15 1985-07-03 SAT (Société Anonyme de Télécommunications),Société Anonyme Memory addressing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0147268A2 (en) * 1983-11-15 1985-07-03 SAT (Société Anonyme de Télécommunications),Société Anonyme Memory addressing circuit

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