JPS57180235A - Driver circuit - Google Patents

Driver circuit

Info

Publication number
JPS57180235A
JPS57180235A JP56066092A JP6609281A JPS57180235A JP S57180235 A JPS57180235 A JP S57180235A JP 56066092 A JP56066092 A JP 56066092A JP 6609281 A JP6609281 A JP 6609281A JP S57180235 A JPS57180235 A JP S57180235A
Authority
JP
Japan
Prior art keywords
voltage
node
turns
gate
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56066092A
Other languages
Japanese (ja)
Inventor
Yoichi Hida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56066092A priority Critical patent/JPS57180235A/en
Publication of JPS57180235A publication Critical patent/JPS57180235A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the occupying area of an IC, by applying a voltage boosted to a voltage which is the sum of a power supply voltage and a threshold voltage, to a load MOS transistor (TR) of each driver. CONSTITUTION:A gate voltage is supplied to a load MOS TR4 of drivers 101 and 102 and the drain and gate of a TR6 charging a capacitor 5 are connected to an output node 20 of a boosting circuit 103. At the rise of a clock phi applied to a terminal 13 of the circuit 103, a node 19 is charged via a C14 to be risen in the level, the TR16 turns on and the level of the node 20 is increased. The charge of the node 19 is discharged at the fall of the clock phi, the TR16 turns off, and the voltage of the node 20 is unchanged. This is repeated, the voltage of the node 20 is increased, and when this is a voltage more than the power supply voltage V+2 threshold voltage VTH, TRs 17 and 18 turns on, and the voltage of the node 20 is clamped to the V+2VTH. When this voltage is supplied to the TR6 of the driver, V+VTH is normally supplied to the gate of the TR4 and the output terminal 2 keeps the level of V.
JP56066092A 1981-04-29 1981-04-29 Driver circuit Pending JPS57180235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56066092A JPS57180235A (en) 1981-04-29 1981-04-29 Driver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56066092A JPS57180235A (en) 1981-04-29 1981-04-29 Driver circuit

Publications (1)

Publication Number Publication Date
JPS57180235A true JPS57180235A (en) 1982-11-06

Family

ID=13305871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56066092A Pending JPS57180235A (en) 1981-04-29 1981-04-29 Driver circuit

Country Status (1)

Country Link
JP (1) JPS57180235A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6316716A (en) * 1986-07-09 1988-01-23 Toshiba Corp Boosting circuit
WO2013098900A1 (en) * 2011-12-28 2013-07-04 パナソニック株式会社 Level shifter, inverter circuit and shift register

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6316716A (en) * 1986-07-09 1988-01-23 Toshiba Corp Boosting circuit
WO2013098900A1 (en) * 2011-12-28 2013-07-04 パナソニック株式会社 Level shifter, inverter circuit and shift register
CN103299547A (en) * 2011-12-28 2013-09-11 松下电器产业株式会社 Level shifter, inverter circuit and shift register
US8649477B2 (en) 2011-12-28 2014-02-11 Panasonic Corporation Level shifter, inverter circuit, and shift register
JPWO2013098900A1 (en) * 2011-12-28 2015-04-30 パナソニック株式会社 Level shifter, inverter circuit and shift register
CN103299547B (en) * 2011-12-28 2017-06-09 株式会社日本有机雷特显示器 Level shifter, inverter circuit and shift register

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