JPS57179915A - Data write-in system in external storage device - Google Patents
Data write-in system in external storage deviceInfo
- Publication number
- JPS57179915A JPS57179915A JP6357981A JP6357981A JPS57179915A JP S57179915 A JPS57179915 A JP S57179915A JP 6357981 A JP6357981 A JP 6357981A JP 6357981 A JP6357981 A JP 6357981A JP S57179915 A JPS57179915 A JP S57179915A
- Authority
- JP
- Japan
- Prior art keywords
- write
- level
- bit
- bits
- encoding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To increase the storage density and the capacity of recording medium of the same size, by assigning a different write-in level to each of input bit, encoding each bit and executing the encoding processing for all the input data. CONSTITUTION:A different write-in level (in this example, full and a half level, two levels in total) with each bit is assigned for encoding to each of a plurality of bits (in this example, two bits) in the order of an input bit signal. A shift register 1 inputs a write-in data Dw to a write-in level designation circuit 2 at each two bits in the order of input bit. This designation circuit 2 designates the write-in level to each bit. Through this designation, a write-in current generating circuit 3 generates a write-in current I2, which is generated for a full level I2F and a half level I2H in accordance with the bits and recorded with heads 4, 5,- n. Thus, recording is made with double density as conventional systems.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6357981A JPS57179915A (en) | 1981-04-27 | 1981-04-27 | Data write-in system in external storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6357981A JPS57179915A (en) | 1981-04-27 | 1981-04-27 | Data write-in system in external storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57179915A true JPS57179915A (en) | 1982-11-05 |
Family
ID=13233304
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6357981A Pending JPS57179915A (en) | 1981-04-27 | 1981-04-27 | Data write-in system in external storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57179915A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54120515A (en) * | 1978-03-10 | 1979-09-19 | Toshiba Corp | Coding system |
-
1981
- 1981-04-27 JP JP6357981A patent/JPS57179915A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54120515A (en) * | 1978-03-10 | 1979-09-19 | Toshiba Corp | Coding system |
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