JPS57176769A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS57176769A
JPS57176769A JP6106881A JP6106881A JPS57176769A JP S57176769 A JPS57176769 A JP S57176769A JP 6106881 A JP6106881 A JP 6106881A JP 6106881 A JP6106881 A JP 6106881A JP S57176769 A JPS57176769 A JP S57176769A
Authority
JP
Japan
Prior art keywords
resist
etched
groove
impurities
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6106881A
Other languages
Japanese (ja)
Inventor
Susumu Muramoto
Kohei Ebara
Manabu Henmi
Seitaro Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6106881A priority Critical patent/JPS57176769A/en
Priority to US06/369,235 priority patent/US4564997A/en
Priority to CA000401294A priority patent/CA1204883A/en
Priority to EP82302044A priority patent/EP0063917B1/en
Priority to DE8282302044T priority patent/DE3271995D1/en
Publication of JPS57176769A publication Critical patent/JPS57176769A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a wiring without difference in steps on a surface, by selectively etching a conductive layer including impurities, which is provided on a semiconductor substrate and withstands high temperature treatment, with an etching mask, and embedding an insulating layer having a specified thickness in an etched cavity. CONSTITUTION:In the application on a bipolar integrated circuit, a resist pattern 9 is formed on a nitride film 3 on an Si substrate 1. With the resist 9 as a mask, the Si3N4 film 3 is etched, and an etched groove having a rectangular cross section without an undercut is provided. Polycrystaline Si 2 including impurities is deposited on the groove at a low temperature, and the etched groove S is buried. At this time deposition is not made on a wall 9' of the resist. The resist 9 is removed, impurities including poly crystalline Si is thermally diffused, and an impurity diffused layer 6 is formed. Thus the wiring having a fine width can be formed without the difference in steps on the surface.
JP6106881A 1981-04-21 1981-04-21 Semiconductor device and manufacture thereof Pending JPS57176769A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP6106881A JPS57176769A (en) 1981-04-21 1981-04-21 Semiconductor device and manufacture thereof
US06/369,235 US4564997A (en) 1981-04-21 1982-04-16 Semiconductor device and manufacturing process thereof
CA000401294A CA1204883A (en) 1981-04-21 1982-04-20 Semiconductor device and manufacturing process thereof
EP82302044A EP0063917B1 (en) 1981-04-21 1982-04-21 Method of manufacturing a semiconductor device
DE8282302044T DE3271995D1 (en) 1981-04-21 1982-04-21 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6106881A JPS57176769A (en) 1981-04-21 1981-04-21 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS57176769A true JPS57176769A (en) 1982-10-30

Family

ID=13160455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6106881A Pending JPS57176769A (en) 1981-04-21 1981-04-21 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57176769A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966483A (en) * 1982-10-08 1984-04-14 Kyokado Eng Co Ltd Grouting method
JPS5966482A (en) * 1982-10-08 1984-04-14 Kyokado Eng Co Ltd Grouting method
JPS59152986A (en) * 1983-02-21 1984-08-31 Kyokado Eng Co Ltd Impregnation method for ground

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144486A (en) * 1974-10-14 1976-04-16 Matsushita Electric Ind Co Ltd mos gatashusekikairosochino seizohoho
JPS5240986A (en) * 1975-09-27 1977-03-30 Toshiba Corp Process for production of semiconductor element
JPS5272571A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Production of semiconductor device
JPS5318958A (en) * 1976-08-05 1978-02-21 Nec Corp Production of semiconductor device
JPS5443466A (en) * 1977-09-12 1979-04-06 Matsushita Electronics Corp Electrode formation method for semiconductor device
JPS5578532A (en) * 1978-12-07 1980-06-13 Matsushita Electronics Corp Formation of electrode for semiconductor device
JPS55102242A (en) * 1978-11-20 1980-08-05 Texas Instruments Inc Method of forming titanium dioxide gate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5144486A (en) * 1974-10-14 1976-04-16 Matsushita Electric Ind Co Ltd mos gatashusekikairosochino seizohoho
JPS5240986A (en) * 1975-09-27 1977-03-30 Toshiba Corp Process for production of semiconductor element
JPS5272571A (en) * 1975-12-15 1977-06-17 Fujitsu Ltd Production of semiconductor device
JPS5318958A (en) * 1976-08-05 1978-02-21 Nec Corp Production of semiconductor device
JPS5443466A (en) * 1977-09-12 1979-04-06 Matsushita Electronics Corp Electrode formation method for semiconductor device
JPS55102242A (en) * 1978-11-20 1980-08-05 Texas Instruments Inc Method of forming titanium dioxide gate
JPS5578532A (en) * 1978-12-07 1980-06-13 Matsushita Electronics Corp Formation of electrode for semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966483A (en) * 1982-10-08 1984-04-14 Kyokado Eng Co Ltd Grouting method
JPS5966482A (en) * 1982-10-08 1984-04-14 Kyokado Eng Co Ltd Grouting method
JPH0235796B2 (en) * 1982-10-08 1990-08-13 Kyokado Eng Co
JPS59152986A (en) * 1983-02-21 1984-08-31 Kyokado Eng Co Ltd Impregnation method for ground
JPH0362751B2 (en) * 1983-02-21 1991-09-26 Kyokado Eng Co

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