JPS57174744A - Interruption processing circuit - Google Patents

Interruption processing circuit

Info

Publication number
JPS57174744A
JPS57174744A JP6011381A JP6011381A JPS57174744A JP S57174744 A JPS57174744 A JP S57174744A JP 6011381 A JP6011381 A JP 6011381A JP 6011381 A JP6011381 A JP 6011381A JP S57174744 A JPS57174744 A JP S57174744A
Authority
JP
Japan
Prior art keywords
interruption
request
given
latch
interruption request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6011381A
Other languages
Japanese (ja)
Inventor
Yutaka Murao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6011381A priority Critical patent/JPS57174744A/en
Publication of JPS57174744A publication Critical patent/JPS57174744A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To avoid the delay for process of interruption, by providing an interruption processing means that accepts one of the interruptions which are in the permissible state for acceptance plus an interruption request latching means with which only the output caused by a program is turned into an interruption factor. CONSTITUTION:An interruption request latch 10 has n-bits and detects the interruption request from either one or both of the rise and fall of a signal, and an interruption request is given by the factor having an output of 1. The contents of the latch 10 are cleared by reset signals LCLR1-ICLRn of n-bits. A latch 20 consisting of an FF of a bit is set only the writing signal LSET produced by the process of a program in case an interruption request is given and then cleared by the reset signal LCLR'. The permissible state of acceptance is decided for the interruption requests given from the latches 10 and 20 and based on the mask information given to an interruption processing circuit 30. Then the request having the highest priority is accepted. In such a way, the delay is avoided for the process of an interruption request.
JP6011381A 1981-04-21 1981-04-21 Interruption processing circuit Pending JPS57174744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6011381A JPS57174744A (en) 1981-04-21 1981-04-21 Interruption processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6011381A JPS57174744A (en) 1981-04-21 1981-04-21 Interruption processing circuit

Publications (1)

Publication Number Publication Date
JPS57174744A true JPS57174744A (en) 1982-10-27

Family

ID=13132729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6011381A Pending JPS57174744A (en) 1981-04-21 1981-04-21 Interruption processing circuit

Country Status (1)

Country Link
JP (1) JPS57174744A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111543A (en) * 1982-12-17 1984-06-27 Nec Corp Interruption controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111543A (en) * 1982-12-17 1984-06-27 Nec Corp Interruption controller

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