JPS57173223A - Phase comparator circuit - Google Patents
Phase comparator circuitInfo
- Publication number
- JPS57173223A JPS57173223A JP56057927A JP5792781A JPS57173223A JP S57173223 A JPS57173223 A JP S57173223A JP 56057927 A JP56057927 A JP 56057927A JP 5792781 A JP5792781 A JP 5792781A JP S57173223 A JPS57173223 A JP S57173223A
- Authority
- JP
- Japan
- Prior art keywords
- outputs
- flip
- flops
- output
- comparator circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To eliminate the need for initialization while speeding up operation by eliminating an astable state by using a setting priority type flip-flop. CONSTITUTION:Waveform shaping circuits 11 and 12, gate circuits 13 and 14, and flip-flops 15 and 16 use AND gates and OR gates respectively and constitute a phase comparator circuit together with inverters G17 and G18, and NAND gates 17 and 18. When an input signal Sig and a reference signal Ref are both 0s, the outputs of the flip-flops 15 and 16 are both 1s and outputs A and B are both 1s. When the input signal Sig is 0, the outputs of the flip-flops 15 and 16 are unchanged, so the output B is 1. Then when the reference signal Ref goes up to 1, the outputs of the gate circuits 13 and 14 are 0s and the flip-flops 15 and 16 are reset to generate outputs 0. In this case, the output B goes up to 1, but the output A is still 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56057927A JPS57173223A (en) | 1981-04-17 | 1981-04-17 | Phase comparator circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56057927A JPS57173223A (en) | 1981-04-17 | 1981-04-17 | Phase comparator circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57173223A true JPS57173223A (en) | 1982-10-25 |
Family
ID=13069632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56057927A Pending JPS57173223A (en) | 1981-04-17 | 1981-04-17 | Phase comparator circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57173223A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01162417A (en) * | 1987-11-20 | 1989-06-26 | Motorola Inc | Frequency synthesizer equipped with digital phase detector having optimum steering and level type locking display |
-
1981
- 1981-04-17 JP JP56057927A patent/JPS57173223A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01162417A (en) * | 1987-11-20 | 1989-06-26 | Motorola Inc | Frequency synthesizer equipped with digital phase detector having optimum steering and level type locking display |
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