JPS57169833A - Digital signal repeater - Google Patents

Digital signal repeater

Info

Publication number
JPS57169833A
JPS57169833A JP5388481A JP5388481A JPS57169833A JP S57169833 A JPS57169833 A JP S57169833A JP 5388481 A JP5388481 A JP 5388481A JP 5388481 A JP5388481 A JP 5388481A JP S57169833 A JPS57169833 A JP S57169833A
Authority
JP
Japan
Prior art keywords
data
signal
output
delivered
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5388481A
Other languages
Japanese (ja)
Inventor
Juichi Maesumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5388481A priority Critical patent/JPS57169833A/en
Publication of JPS57169833A publication Critical patent/JPS57169833A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To reduce the load on the software and to realize a high-speed transfer of data, by connecting the input/output devices of different transfer end formats to the same reference digital bus and detecting the transfer end code with an exclusive circuit. CONSTITUTION:The command data RCMD is set to a register 312 synchronously with the control signal CCMD given from a CPU not shown in the diagram. Then the output data is set to a register 313 via the input/output bus DBUS and a receiver 310 and based on the writing signal CDAV, and the output RWO- 7 is delivered the standard digital bus CBUS via a driver 319. At the same time, the status signal BUSY showing the data transfer state is delivered to the CPU from a writing control circuit 314. When the data transmitting process is over between the input/output devices connected to the bus CBUS, the signal SHE is delivered from a transmission control circuit 320, and the signal BUSY from the circuit 314 is reset.
JP5388481A 1981-04-10 1981-04-10 Digital signal repeater Pending JPS57169833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5388481A JPS57169833A (en) 1981-04-10 1981-04-10 Digital signal repeater

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5388481A JPS57169833A (en) 1981-04-10 1981-04-10 Digital signal repeater

Publications (1)

Publication Number Publication Date
JPS57169833A true JPS57169833A (en) 1982-10-19

Family

ID=12955159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5388481A Pending JPS57169833A (en) 1981-04-10 1981-04-10 Digital signal repeater

Country Status (1)

Country Link
JP (1) JPS57169833A (en)

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