JPS57164346A - Duplex system microcomputer device - Google Patents
Duplex system microcomputer deviceInfo
- Publication number
- JPS57164346A JPS57164346A JP56049861A JP4986181A JPS57164346A JP S57164346 A JPS57164346 A JP S57164346A JP 56049861 A JP56049861 A JP 56049861A JP 4986181 A JP4986181 A JP 4986181A JP S57164346 A JPS57164346 A JP S57164346A
- Authority
- JP
- Japan
- Prior art keywords
- slave
- result
- main
- processing
- status display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To operate independently one microcomputer automatically if another computer has failed, by providing a data transmission/reception device and a status display transmission/reception device mutually connecting two sets of micrcomputers and operating them synchronizingly while monitoring the both. CONSTITUTION:When status display devices 10 and 20 are initially set and microprocessors 11 and 21 are operated respectively as the main and slave systems, input data from an input device 3 are fetched to the main and the slave systems simultaneously, and they are processed repectively and the result of processing is transferred from the slave system 21 to the main system with data transmission/reception devices 14 and 24. The main system 11 makes coincidence check for the result of processing of the main and slave systems, and when they are coincident, the result is transmitted to an output device 4. If not coincident, self-diagnosis is made. When the result of diagnosis is normal, the result of processing is judged as normal, the slave system 21 is regarded as failure and it is informed to the slave system 21 with status display transmission/reception devices 10 and 20, the slave system failure information is transmitted to an output device 14 and it is informed to the operator. The slave system 21 stops the processing of itself by it and the operation is made through the instruction of the operator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56049861A JPS57164346A (en) | 1981-04-01 | 1981-04-01 | Duplex system microcomputer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56049861A JPS57164346A (en) | 1981-04-01 | 1981-04-01 | Duplex system microcomputer device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57164346A true JPS57164346A (en) | 1982-10-08 |
Family
ID=12842827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56049861A Pending JPS57164346A (en) | 1981-04-01 | 1981-04-01 | Duplex system microcomputer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57164346A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH054261U (en) * | 1991-07-01 | 1993-01-22 | 日本電気株式会社 | CPU protection method |
JPH05250200A (en) * | 1992-03-09 | 1993-09-28 | Nec Corp | Bus confounding circuit |
US5870301A (en) * | 1995-03-30 | 1999-02-09 | Fujitsu Limited | System control apparatus including a master control unit and a slave control unit which maintain coherent information |
-
1981
- 1981-04-01 JP JP56049861A patent/JPS57164346A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH054261U (en) * | 1991-07-01 | 1993-01-22 | 日本電気株式会社 | CPU protection method |
JPH05250200A (en) * | 1992-03-09 | 1993-09-28 | Nec Corp | Bus confounding circuit |
US5870301A (en) * | 1995-03-30 | 1999-02-09 | Fujitsu Limited | System control apparatus including a master control unit and a slave control unit which maintain coherent information |
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