JPS57162171A - Magnetic bubble memory chip - Google Patents
Magnetic bubble memory chipInfo
- Publication number
- JPS57162171A JPS57162171A JP4385981A JP4385981A JPS57162171A JP S57162171 A JPS57162171 A JP S57162171A JP 4385981 A JP4385981 A JP 4385981A JP 4385981 A JP4385981 A JP 4385981A JP S57162171 A JPS57162171 A JP S57162171A
- Authority
- JP
- Japan
- Prior art keywords
- double
- period pattern
- length period
- minor loop
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0808—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation
- G11C19/0816—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation using a rotating or alternating coplanar magnetic field
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To input/output 1 bit information by 1 bit transfer and to improve the data transfer rate by constituting an I/O track corresponding to a minor loop by a 4 double-length period pattern. CONSTITUTION:An I/O track such as a replicate 6 and a swap gate 7 corresponding to a minor loop 1 with overlapped construction is constituted by a 4 double-length period pattern 10 and each minor loop 1 is bonded by the 4 double- length period pattern 10 of 1 bit per minor loop. The constitution makes it possible to input/output 1 bit information by 1 bit transfer, increasing the data transfer rate 4 times to the 1 double-length period pattern and twice to the 2 double-length period pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4385981A JPS57162171A (en) | 1981-03-27 | 1981-03-27 | Magnetic bubble memory chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4385981A JPS57162171A (en) | 1981-03-27 | 1981-03-27 | Magnetic bubble memory chip |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57162171A true JPS57162171A (en) | 1982-10-05 |
JPS611830B2 JPS611830B2 (en) | 1986-01-20 |
Family
ID=12675421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4385981A Granted JPS57162171A (en) | 1981-03-27 | 1981-03-27 | Magnetic bubble memory chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57162171A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0392025U (en) * | 1989-10-20 | 1991-09-19 | ||
JPH03124563U (en) * | 1990-03-30 | 1991-12-17 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5580878A (en) * | 1978-12-08 | 1980-06-18 | Fujitsu Ltd | Magnetic bubble memory device |
JPS5616987A (en) * | 1979-07-17 | 1981-02-18 | Fujitsu Ltd | Magnetic bubble memory unit |
JPS5619579A (en) * | 1979-07-17 | 1981-02-24 | Fujitsu Ltd | Exchange circuit of bubble magnetic domain |
-
1981
- 1981-03-27 JP JP4385981A patent/JPS57162171A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5580878A (en) * | 1978-12-08 | 1980-06-18 | Fujitsu Ltd | Magnetic bubble memory device |
JPS5616987A (en) * | 1979-07-17 | 1981-02-18 | Fujitsu Ltd | Magnetic bubble memory unit |
JPS5619579A (en) * | 1979-07-17 | 1981-02-24 | Fujitsu Ltd | Exchange circuit of bubble magnetic domain |
Also Published As
Publication number | Publication date |
---|---|
JPS611830B2 (en) | 1986-01-20 |
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