JPS57161916A - Device for data transfer between input and output device using offset system and block multiplexer channel - Google Patents

Device for data transfer between input and output device using offset system and block multiplexer channel

Info

Publication number
JPS57161916A
JPS57161916A JP4560781A JP4560781A JPS57161916A JP S57161916 A JPS57161916 A JP S57161916A JP 4560781 A JP4560781 A JP 4560781A JP 4560781 A JP4560781 A JP 4560781A JP S57161916 A JPS57161916 A JP S57161916A
Authority
JP
Japan
Prior art keywords
data
input
register
buffer
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4560781A
Other languages
Japanese (ja)
Inventor
Takashi Owaki
Kosuke Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4560781A priority Critical patent/JPS57161916A/en
Publication of JPS57161916A publication Critical patent/JPS57161916A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To take transmission data of an input/output device into a channel surely to process data between the input/output device and the channel in a high speed at every constant time successively, by providing two registers in the channel. CONSTITUTION:When an operation start instruction is issued from CPU to a block multiplexer channel (BMC)1, the BMC1 is operated. Data S1 and a transmission report signal arrive at the BMC1 through a data bus 4 and a signal line 2 respectively at a time t0 and are input to a register 11. Data S1 is held because the data processing is executed in a buffer 13, and data S1 is transfered to the register 13 when the buffer 13 becomes idle, and contents of the register 11 are cleared. Data d1 transmitted before data S1 is stored in a register 12 together with the transmission report signal similarly. Data d1 is held in the register 12 because the buffer 13 is full of data S1. After the occupation of the buffer 13 by data S1, data d1 is transferred to the buffer 13.
JP4560781A 1981-03-30 1981-03-30 Device for data transfer between input and output device using offset system and block multiplexer channel Pending JPS57161916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4560781A JPS57161916A (en) 1981-03-30 1981-03-30 Device for data transfer between input and output device using offset system and block multiplexer channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4560781A JPS57161916A (en) 1981-03-30 1981-03-30 Device for data transfer between input and output device using offset system and block multiplexer channel

Publications (1)

Publication Number Publication Date
JPS57161916A true JPS57161916A (en) 1982-10-05

Family

ID=12724040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4560781A Pending JPS57161916A (en) 1981-03-30 1981-03-30 Device for data transfer between input and output device using offset system and block multiplexer channel

Country Status (1)

Country Link
JP (1) JPS57161916A (en)

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