JPS57152284A - Television signal system discriminating circuit - Google Patents

Television signal system discriminating circuit

Info

Publication number
JPS57152284A
JPS57152284A JP3684481A JP3684481A JPS57152284A JP S57152284 A JPS57152284 A JP S57152284A JP 3684481 A JP3684481 A JP 3684481A JP 3684481 A JP3684481 A JP 3684481A JP S57152284 A JPS57152284 A JP S57152284A
Authority
JP
Japan
Prior art keywords
signal
inputted
dividing
synchronizing signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3684481A
Other languages
Japanese (ja)
Inventor
Sadanobu Ishida
Satoshi Kunii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3684481A priority Critical patent/JPS57152284A/en
Publication of JPS57152284A publication Critical patent/JPS57152284A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/642—Multi-standard receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)

Abstract

PURPOSE:To discriminate TV signal systems by a simple configuration by discriminating a TV signal system from the dividing condition of a variable dividing means switching the TV signal system to the dividing ratio corresponding to plural TV signal systems. CONSTITUTION:A TV signal of an NTSC or a PAL/SEC system is inputted to a synchronizing signal separation circuit 2 and a synchronizing signal E is separated. A pulse signal F having the frequency twice that of a horizontal synchronizing signal is formed from the synchronizing signal E by PLL 3. The signal E is inputted to a 2-stage shift register 4 and a signal I corresponding to the vertical synchronizing signal is obtained from the 1st and 2nd stage output signals G, H. When a signal belonging to the NTSC system is inputted to a terminal 1, a selector 10 selects and AND gate to decode 524, so that the output from a NAND gate is turned to ''0'', an AND gate stops the signal I and turns its output to ''0'' and a FF13 does not change its status. A counter 7 holds the dividing of 525. When a signal belonging to the PAL system is inputted, the same operation is also performed.
JP3684481A 1981-03-13 1981-03-13 Television signal system discriminating circuit Pending JPS57152284A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3684481A JPS57152284A (en) 1981-03-13 1981-03-13 Television signal system discriminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3684481A JPS57152284A (en) 1981-03-13 1981-03-13 Television signal system discriminating circuit

Publications (1)

Publication Number Publication Date
JPS57152284A true JPS57152284A (en) 1982-09-20

Family

ID=12481064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3684481A Pending JPS57152284A (en) 1981-03-13 1981-03-13 Television signal system discriminating circuit

Country Status (1)

Country Link
JP (1) JPS57152284A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6086967A (en) * 1983-09-15 1985-05-16 プレツシイ・オーバーシーズ・リミテツド Circuit for converting one television scanning reference to another scanning reference
JPS61141284A (en) * 1984-12-14 1986-06-28 Hitachi Ltd System discriminating systemin multiplex tv-receiver
EP0511798A2 (en) * 1991-04-30 1992-11-04 The Grass Valley Group, Inc. Clock generation circuit for multistandard serial digital video with automatic format identification

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6086967A (en) * 1983-09-15 1985-05-16 プレツシイ・オーバーシーズ・リミテツド Circuit for converting one television scanning reference to another scanning reference
JPS61141284A (en) * 1984-12-14 1986-06-28 Hitachi Ltd System discriminating systemin multiplex tv-receiver
EP0511798A2 (en) * 1991-04-30 1992-11-04 The Grass Valley Group, Inc. Clock generation circuit for multistandard serial digital video with automatic format identification

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