JPS57143968A - Channel test system - Google Patents
Channel test systemInfo
- Publication number
- JPS57143968A JPS57143968A JP2840581A JP2840581A JPS57143968A JP S57143968 A JPS57143968 A JP S57143968A JP 2840581 A JP2840581 A JP 2840581A JP 2840581 A JP2840581 A JP 2840581A JP S57143968 A JPS57143968 A JP S57143968A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- multifrequency
- multifrequency signal
- mfs
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
PURPOSE:To confirm the normalcy of a channel without using any special testing jig by utilizing a multifrequency signal transmitter and a receiver equipped to a switchboard, and by using a multifrequency signal that they transmit and receive. CONSTITUTION:A central processor controls the closure of a channel extending from a multifrequency signal transmitter MFS to a multifrequency receiver MFR through a point P to be tested in a digital channel network TDNW. Under this control, the MFS sends out the multifrequency signal continuously for a certain time. This multifrequency signal is switched by, e.g., eight bits at each time at the point P of the closed channel, and the resulting signal is sent to and received by the MFS. During this testing operation, the MFR when the tested channel is normal receives a sent PCM multifrequency signal as it is in a bit sequence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2840581A JPS57143968A (en) | 1981-03-02 | 1981-03-02 | Channel test system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2840581A JPS57143968A (en) | 1981-03-02 | 1981-03-02 | Channel test system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57143968A true JPS57143968A (en) | 1982-09-06 |
JPH0133998B2 JPH0133998B2 (en) | 1989-07-17 |
Family
ID=12247748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2840581A Granted JPS57143968A (en) | 1981-03-02 | 1981-03-02 | Channel test system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57143968A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6181499B1 (en) | 1998-04-07 | 2001-01-30 | International Business Machines Corporation | Method and apparatus for testing the digital read channel circuit of a data storage device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5434706A (en) * | 1977-08-05 | 1979-03-14 | Int Standard Electric Corp | Communication facility continuity tester |
JPS5577268A (en) * | 1978-12-07 | 1980-06-10 | Toshiba Corp | Channel test system |
-
1981
- 1981-03-02 JP JP2840581A patent/JPS57143968A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5434706A (en) * | 1977-08-05 | 1979-03-14 | Int Standard Electric Corp | Communication facility continuity tester |
JPS5577268A (en) * | 1978-12-07 | 1980-06-10 | Toshiba Corp | Channel test system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6181499B1 (en) | 1998-04-07 | 2001-01-30 | International Business Machines Corporation | Method and apparatus for testing the digital read channel circuit of a data storage device |
Also Published As
Publication number | Publication date |
---|---|
JPH0133998B2 (en) | 1989-07-17 |
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