JPS57139864A - Memory extension system - Google Patents
Memory extension systemInfo
- Publication number
- JPS57139864A JPS57139864A JP56025838A JP2583881A JPS57139864A JP S57139864 A JPS57139864 A JP S57139864A JP 56025838 A JP56025838 A JP 56025838A JP 2583881 A JP2583881 A JP 2583881A JP S57139864 A JPS57139864 A JP S57139864A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- line
- high rank
- rank address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
Abstract
PURPOSE:To obtain an address of a memory by providing a register in the memory, and combining a low rank address and a high rank address when the high rank address written in advances and the high rank address from a microprocessor have coincided with a designated address. CONSTITUTION:A memory read signal MEMR line 61, a memory write signal MEMW line 62 and an 8 bit data bus 4 are connected to a memory 7, and 8 bit register 8 is connected to the 8 bit data bus 4, and a high rank address is written by an I/O write signal IOW. An output of the 8 bit register 8 is combined with an address of a low rank address bus line 51, and its output is connected to the memory 7 by an address line 10. Also, a decoder 9 is connected to a high rank address bus line 52, and its output is connected to a selecting terminal (s) of the memory 7. The memory 7 reads or writes through the 8 bit data bus 4 by a memory read signal or a memory write signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56025838A JPS57139864A (en) | 1981-02-24 | 1981-02-24 | Memory extension system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56025838A JPS57139864A (en) | 1981-02-24 | 1981-02-24 | Memory extension system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57139864A true JPS57139864A (en) | 1982-08-30 |
Family
ID=12176991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56025838A Pending JPS57139864A (en) | 1981-02-24 | 1981-02-24 | Memory extension system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57139864A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133449A (en) * | 1984-11-30 | 1986-06-20 | Tokyo Juki Ind Co Ltd | Access method to external memory in computer |
JPS625354U (en) * | 1985-06-21 | 1987-01-13 | ||
JP2001222464A (en) * | 2000-02-09 | 2001-08-17 | Fujitsu Ltd | Data input/output system |
-
1981
- 1981-02-24 JP JP56025838A patent/JPS57139864A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133449A (en) * | 1984-11-30 | 1986-06-20 | Tokyo Juki Ind Co Ltd | Access method to external memory in computer |
JPS625354U (en) * | 1985-06-21 | 1987-01-13 | ||
JP2001222464A (en) * | 2000-02-09 | 2001-08-17 | Fujitsu Ltd | Data input/output system |
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