JPS57137948A - Automatic error correction system - Google Patents

Automatic error correction system

Info

Publication number
JPS57137948A
JPS57137948A JP56023528A JP2352881A JPS57137948A JP S57137948 A JPS57137948 A JP S57137948A JP 56023528 A JP56023528 A JP 56023528A JP 2352881 A JP2352881 A JP 2352881A JP S57137948 A JPS57137948 A JP S57137948A
Authority
JP
Japan
Prior art keywords
data
control memory
circuit
read
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56023528A
Other languages
Japanese (ja)
Inventor
Yasuo Fujihira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56023528A priority Critical patent/JPS57137948A/en
Publication of JPS57137948A publication Critical patent/JPS57137948A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To select a read-out data whose normality is high and also to correct the error of a lot of bits, and to improve the reliability, by doubling a data storage means and utilizing detecting mechanism of a parity error. CONSTITUTION:Data which should have the same contents are read out from the first control memory 3 and the second control memory 4, respectively. Each read-out data is compared and decided at every bit by a comparing circuit 5 as to whether each data is in coincidence or not. As for the data read out from the first control memory 3, and the data from the second control memory 4, each parity check is executed by a parity checking circuit 6 and a parity checking circuit 7, respectively. A selecting circuit 8 selects one of the first control memory 3 side or the second control memory 4 side at every byte by an output of a selection deciding circuit 15, and outputs a selected read-out data and a result of parity check. An output of the selecting circuit 8 is fed to an input to a correcting circuit 17.
JP56023528A 1981-02-19 1981-02-19 Automatic error correction system Pending JPS57137948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56023528A JPS57137948A (en) 1981-02-19 1981-02-19 Automatic error correction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56023528A JPS57137948A (en) 1981-02-19 1981-02-19 Automatic error correction system

Publications (1)

Publication Number Publication Date
JPS57137948A true JPS57137948A (en) 1982-08-25

Family

ID=12112943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56023528A Pending JPS57137948A (en) 1981-02-19 1981-02-19 Automatic error correction system

Country Status (1)

Country Link
JP (1) JPS57137948A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213128A (en) * 1985-07-10 1987-01-21 Pioneer Electronic Corp Error correction system
JP2008158804A (en) * 2006-12-22 2008-07-10 Nec Corp Memory controller, computer and data reading method
JP2010244093A (en) * 2009-04-01 2010-10-28 Seiko Epson Corp Memory device, circuit board, liquid receptacle, method of controlling nonvolatile data memory section, and system including memory device detachably attachable to host circuit
US8782326B2 (en) 2009-04-01 2014-07-15 Seiko Epson Corporation Memory device and system including a memory device electronically connectable to a host circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213128A (en) * 1985-07-10 1987-01-21 Pioneer Electronic Corp Error correction system
JPH041530B2 (en) * 1985-07-10 1992-01-13 Pioneer Electronic Corp
JP2008158804A (en) * 2006-12-22 2008-07-10 Nec Corp Memory controller, computer and data reading method
JP2010244093A (en) * 2009-04-01 2010-10-28 Seiko Epson Corp Memory device, circuit board, liquid receptacle, method of controlling nonvolatile data memory section, and system including memory device detachably attachable to host circuit
US8627190B2 (en) 2009-04-01 2014-01-07 Seiko Epson Corporation Memory device, circuit board, liquid receptacle, method of controlling a nonvolatile data memory section, and system including a memory device detachably connectable to a host circuit
US8782326B2 (en) 2009-04-01 2014-07-15 Seiko Epson Corporation Memory device and system including a memory device electronically connectable to a host circuit

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