JPS57132448A - Data transmitting device - Google Patents
Data transmitting deviceInfo
- Publication number
- JPS57132448A JPS57132448A JP56018528A JP1852881A JPS57132448A JP S57132448 A JPS57132448 A JP S57132448A JP 56018528 A JP56018528 A JP 56018528A JP 1852881 A JP1852881 A JP 1852881A JP S57132448 A JPS57132448 A JP S57132448A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- bit
- data
- transmission
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To simplify the constitution and to increase the transmission efficiency, by converting a frame bit in frame information into a specific frame bit representing the start of data or end of data, as required. CONSTITUTION:Transferred information on a transmitter 101 is received with a line receiver 102, frame bit is detected from a frame information outputted from the receiver 102 at a frame synchronizing circuit 201, and when the bit is a specific bit representing the start or end of data, a START or END signal is added to a reception control section 202. The data bit in each frame is selected and a data clock signal is added to an S/P converter 106, and the data bit is converted in parallel at the converter 106. The reception controlling section 202 monitors the START or END signal, controls a frame bit conversion circuit 204 via a transmission control section 203, and the frame bit conversion is made depending if the device itself is at transmission or reception state, allowing to increase the transmission efficiency.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56018528A JPS57132448A (en) | 1981-02-10 | 1981-02-10 | Data transmitting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56018528A JPS57132448A (en) | 1981-02-10 | 1981-02-10 | Data transmitting device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57132448A true JPS57132448A (en) | 1982-08-16 |
Family
ID=11974120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56018528A Pending JPS57132448A (en) | 1981-02-10 | 1981-02-10 | Data transmitting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132448A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05652U (en) * | 1991-06-20 | 1993-01-08 | 出光石油化学株式会社 | Container |
-
1981
- 1981-02-10 JP JP56018528A patent/JPS57132448A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05652U (en) * | 1991-06-20 | 1993-01-08 | 出光石油化学株式会社 | Container |
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