JPS57132244A - Series to parallel signal converting circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by reducing the freauency of a clock supplied to an FF to 1/2-1/4 as high as a usual one by expanding series signals to stages of registers successively in parallel, and by latching the contents of the registers at prescribed timing. CONSTITUTION:A high-speed series signal inputted to a series-parallel circuit is read in FFs Fa and Fb at a speed a half as high as that of a clock signal CLK1 by mutually 180 deg. out-of-phase clock signals CL11 and CL22. The contents of the FFFa are read in FFs F6' and F7' at a speed a half as high as that of the signal CL11 by mutually 180 deg. out-of-phase clock signals CL111 and CL112 to be transferred to FFs F1' and F3'. Similarly, the contents of the FFFb are read in FFs F6' and F8' by clock signals CL121 and CL122 to be transferred to FFs F2' and F4'. Further, the contents of the FFs F1'-F8' are latched by a latch circuit by clock signals CL to obtain an 8-bit parallel signal.