JPS5712499A - Prom read/write control device - Google Patents
Prom read/write control deviceInfo
- Publication number
- JPS5712499A JPS5712499A JP8603880A JP8603880A JPS5712499A JP S5712499 A JPS5712499 A JP S5712499A JP 8603880 A JP8603880 A JP 8603880A JP 8603880 A JP8603880 A JP 8603880A JP S5712499 A JPS5712499 A JP S5712499A
- Authority
- JP
- Japan
- Prior art keywords
- register
- circuit
- stored
- coincidence
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE:To obtain a P-ROM having a sufficient tolerance, by securing a previous and assured checking for an access time with addition of a small number of circuit parts. CONSTITUTION:The address information of a PROM22 is delivered to an address bus AB from an RAM16, and accordingly the logic state of the address information varies. This change is conveyed to a trigger circuit 32. Detecting the change, the circuit 32 delivers a pulse having a short set time width to a line 39. As a result, the output state of the ROM22 after lapse of the pulse time is stored temporarily in a latching circuit 33. Then the output of the circuit 33 is stored in register A in a CPU14. And then the output state of ROM22 in a lapse of a sufficient time after an access is stored in register B. The information obtained from the RAM16 is compared with the information stored in register A and then with the information stored in register B if no coincidence is obtained in the first comparison. If a coincidence is obtained, an incorrect access time is decided. While a comparison is given to the contents between the registers A and B in case no coincidence is obtained. Then a prescribed process is carried out.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8603880A JPS5712499A (en) | 1980-06-24 | 1980-06-24 | Prom read/write control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8603880A JPS5712499A (en) | 1980-06-24 | 1980-06-24 | Prom read/write control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5712499A true JPS5712499A (en) | 1982-01-22 |
Family
ID=13875495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8603880A Pending JPS5712499A (en) | 1980-06-24 | 1980-06-24 | Prom read/write control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5712499A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6378400A (en) * | 1986-09-19 | 1988-04-08 | Fujitsu Ltd | Ram test system |
-
1980
- 1980-06-24 JP JP8603880A patent/JPS5712499A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6378400A (en) * | 1986-09-19 | 1988-04-08 | Fujitsu Ltd | Ram test system |
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