JPS57112158A - Code converting circuit - Google Patents

Code converting circuit

Info

Publication number
JPS57112158A
JPS57112158A JP55187328A JP18732880A JPS57112158A JP S57112158 A JPS57112158 A JP S57112158A JP 55187328 A JP55187328 A JP 55187328A JP 18732880 A JP18732880 A JP 18732880A JP S57112158 A JPS57112158 A JP S57112158A
Authority
JP
Japan
Prior art keywords
circuit
nrz data
nrz
output
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55187328A
Other languages
Japanese (ja)
Inventor
Hisanobu Fujimoto
Noriyuki Kutsuwada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187328A priority Critical patent/JPS57112158A/en
Publication of JPS57112158A publication Critical patent/JPS57112158A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To simplify the NRZ-DMI code converting circuit, by utilizing the character of the diagram of state transition of the DMI code to convert the NRZ code to the DMI code. CONSTITUTION:NRZ data (b) and a clock signal (a) are inputted to a circuit A which has the output inverted each time NRZ data (b) generates ''1'', and a signal (c) indicating the state of the conversion mode appears in the output of the circuit A. Meanwhile, NRZ data (b) and the clock signal (a) are inputted to a circuit B, and the clock signal (a) is outputted as it is when NRZ data (b) is ''1'', and ''1'' is outputted when NRZ data (b) is ''1'', and thus, one state of the conversion mode is realized. When exclusive OR between the output (c) of the circuit A and an output (d) of the circuit B is operated, the conversion mode is switched each time input NRZ data (b) becomes ''1'' , and thus, a DMI code (e) is outputted.
JP55187328A 1980-12-29 1980-12-29 Code converting circuit Pending JPS57112158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187328A JPS57112158A (en) 1980-12-29 1980-12-29 Code converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187328A JPS57112158A (en) 1980-12-29 1980-12-29 Code converting circuit

Publications (1)

Publication Number Publication Date
JPS57112158A true JPS57112158A (en) 1982-07-13

Family

ID=16204072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187328A Pending JPS57112158A (en) 1980-12-29 1980-12-29 Code converting circuit

Country Status (1)

Country Link
JP (1) JPS57112158A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989008356A1 (en) * 1988-03-04 1989-09-08 Fujitsu Limited Method and apparatus for modulating a semiconductor laser
JPH0575473A (en) * 1992-03-04 1993-03-26 Nippon Telegr & Teleph Corp <Ntt> Encoder
JPH05315966A (en) * 1989-12-12 1993-11-26 Electron & Telecommun Res Inst Nrz/cmi(ii) code conversion device
JPH0728267B1 (en) * 1988-03-04 1995-03-29 Fujitsu Ltd

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989008356A1 (en) * 1988-03-04 1989-09-08 Fujitsu Limited Method and apparatus for modulating a semiconductor laser
US5073331A (en) * 1988-03-04 1991-12-17 Fujitsu Limited Modulation method for use in a semiconductor laser and an apparatus therefor
JPH0728267B1 (en) * 1988-03-04 1995-03-29 Fujitsu Ltd
JPH05315966A (en) * 1989-12-12 1993-11-26 Electron & Telecommun Res Inst Nrz/cmi(ii) code conversion device
JPH0575473A (en) * 1992-03-04 1993-03-26 Nippon Telegr & Teleph Corp <Ntt> Encoder

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