JPS57111721A - Bus driving control circuit - Google Patents

Bus driving control circuit

Info

Publication number
JPS57111721A
JPS57111721A JP55187839A JP18783980A JPS57111721A JP S57111721 A JPS57111721 A JP S57111721A JP 55187839 A JP55187839 A JP 55187839A JP 18783980 A JP18783980 A JP 18783980A JP S57111721 A JPS57111721 A JP S57111721A
Authority
JP
Japan
Prior art keywords
buffers
driving control
inputs
control signal
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55187839A
Other languages
Japanese (ja)
Inventor
Masanori Kajiwara
Takao Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187839A priority Critical patent/JPS57111721A/en
Publication of JPS57111721A publication Critical patent/JPS57111721A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To output always <=1 driving control signal to prevent the destruction of circuits of tristate buffers, by providing a gate circuit on a driving control signal line so that tristate buffers are not operated simultaneously. CONSTITUTION:Three data inputs d1-d3 are inputted to a data bus 1 through tristate driving buffers 2-1-2-3, and the output of these inputs d1-d3 to the bus 1 is controlled by driving signals C1-C3 from driving control signal lines 4-1-4-3. These signals C1-C3 are inputted respective one inputs of AND circuits 3-1-3-3, and outputs on signal lines 4-1-4-3 are applied to the other inputs through a gate circuit consisting of resistances R1-R3, diodes D1-D4, a transistor TR1, etc. By signals C1-C3, buffers 2-1-2-3 are forcedly inhibited from being driven simultaneously, thus preventing the destruction of circuits connected to buffers 2-1-2-3.
JP55187839A 1980-12-29 1980-12-29 Bus driving control circuit Pending JPS57111721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187839A JPS57111721A (en) 1980-12-29 1980-12-29 Bus driving control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187839A JPS57111721A (en) 1980-12-29 1980-12-29 Bus driving control circuit

Publications (1)

Publication Number Publication Date
JPS57111721A true JPS57111721A (en) 1982-07-12

Family

ID=16213126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187839A Pending JPS57111721A (en) 1980-12-29 1980-12-29 Bus driving control circuit

Country Status (1)

Country Link
JP (1) JPS57111721A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041159A (en) * 1983-08-13 1985-03-04 Matsushita Electric Works Ltd Structure of external input/output bus
JPH0346016A (en) * 1989-07-13 1991-02-27 Fujitsu Ltd Bus control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041159A (en) * 1983-08-13 1985-03-04 Matsushita Electric Works Ltd Structure of external input/output bus
JPH0346016A (en) * 1989-07-13 1991-02-27 Fujitsu Ltd Bus control system

Similar Documents

Publication Publication Date Title
GB1527910A (en) Burner control systems
IE813069L (en) Buffer circuit
JPS57111721A (en) Bus driving control circuit
DE3765695D1 (en) PROGRAMMABLE CIRCUIT ARRANGEMENT.
JPS554178A (en) Information control system
JPS57129537A (en) Programmable array circuit
GB1412156A (en) Pulse amplitude-modulated signal transmission systems
JPS5725734A (en) Party call receiver
JPS57147703A (en) Input and output controller
JPS57191753A (en) Register controlling system
JPS57114946A (en) Microprogram controller
JPS57178542A (en) Integrated circuit
JPS56152031A (en) Bus controller
JPS5750134A (en) Output circuit
JPS5487442A (en) Multi-gate control circuit
JPS5644882A (en) Time generating device
KR930003624A (en) Telephone Number Transfer System
JPS6439698A (en) Shift circuit
JPS57161940A (en) Central processing device
JPS57124942A (en) Logical circuit
JPS5760422A (en) Data transfer controlling system
JPS57106229A (en) Cmos multiinput storage circuit
JPS5795184A (en) Inverter driving circuit
JPS54113236A (en) Logical signal transfer circuit
JPS5769449A (en) Digital arithmetic circuit