JPS57110093A - Controlling method for inverter - Google Patents
Controlling method for inverterInfo
- Publication number
- JPS57110093A JPS57110093A JP55183805A JP18380580A JPS57110093A JP S57110093 A JPS57110093 A JP S57110093A JP 55183805 A JP55183805 A JP 55183805A JP 18380580 A JP18380580 A JP 18380580A JP S57110093 A JPS57110093 A JP S57110093A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- cpu9
- time duration
- signal
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/0077—Characterised by the use of a particular software algorithm
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Ac Motors In General (AREA)
- Inverter Devices (AREA)
Abstract
PURPOSE:To maximize the oprating efficiency of an inverter irrespective of the set rotating speed and the magnitude of a load without necessity of an additional circuit by simply calculating without storing a pulse pattern to obtain a pulse width modulation waveform. CONSTITUTION:A microprocessor CPU9 reads the number n3 of basic pulses determined by the maximum efficiency operating frequency for each operating frequency of an operating frequency setting unit 8 from a memory ROM10, and sets it to an external frequency divider 12. On the other hand, since a basic oscillation frequency f0 from a reference oscillator 11 is applied to the frequency divider 12, the frequency f0 is divided by 1/n3, and is inputted to an external timer 13. The CPU9 unloads the ON time duration of voltage application and OFF time duration from a memory RAM14 and outputs them to a gate circuit 15, thereby controlling a main circuit controller 7. The CPU9 further calculates the time duration of a gate signal from the period of time up to the time up of the timer 13, the signal of a rotating speed detector 3 and the signal from the unit 8, and stores it in the RAM14.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55183805A JPS57110093A (en) | 1980-12-26 | 1980-12-26 | Controlling method for inverter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55183805A JPS57110093A (en) | 1980-12-26 | 1980-12-26 | Controlling method for inverter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57110093A true JPS57110093A (en) | 1982-07-08 |
Family
ID=16142196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55183805A Pending JPS57110093A (en) | 1980-12-26 | 1980-12-26 | Controlling method for inverter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57110093A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1984001865A1 (en) * | 1982-11-02 | 1984-05-10 | Fanuc Ltd | Controller for ac motor |
-
1980
- 1980-12-26 JP JP55183805A patent/JPS57110093A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1984001865A1 (en) * | 1982-11-02 | 1984-05-10 | Fanuc Ltd | Controller for ac motor |
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