JPS57106936A - Interface controlling system - Google Patents

Interface controlling system

Info

Publication number
JPS57106936A
JPS57106936A JP18355480A JP18355480A JPS57106936A JP S57106936 A JPS57106936 A JP S57106936A JP 18355480 A JP18355480 A JP 18355480A JP 18355480 A JP18355480 A JP 18355480A JP S57106936 A JPS57106936 A JP S57106936A
Authority
JP
Japan
Prior art keywords
output
input
equipment
signal
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18355480A
Other languages
Japanese (ja)
Inventor
Shinichi Kubo
Katsuichi Hirowatari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18355480A priority Critical patent/JPS57106936A/en
Publication of JPS57106936A publication Critical patent/JPS57106936A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To control a synchronous type input and output equipment and an interlocking type input and output equipment by the same input and output controller, by sending a response signal from the synchronous type input and output equipment. CONSTITUTION:To select one of input and output equipments 1-1-1-4, an input and output controller 2 sends an input-and-output-equipment selection signal to corresponding signal lines 8-1-8-4. When the selection signal indicates the interlocking type input and output equipment 1-3 or 1-4, a response generation part 5-1 or 5-2 sends a response signal B to an interface control IFC part 3 on the basis of an enable signal 7. The response signal B is synchronized by the IFC part 3 to perform data transfer between the controller 2 and input and output equipment 1-3 or 1-4. When the selection signal indicates the synchronous type input and output device 1-1 or 1-2, the selection signal is inverted by an NOT gate 4-1 or 4-2 to be inputted as a response signal A to the IFC3, and it is converted into a response signal to enable the transfer of data between the controller 2 and equipment 1-1 or 1-2.
JP18355480A 1980-12-24 1980-12-24 Interface controlling system Pending JPS57106936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18355480A JPS57106936A (en) 1980-12-24 1980-12-24 Interface controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18355480A JPS57106936A (en) 1980-12-24 1980-12-24 Interface controlling system

Publications (1)

Publication Number Publication Date
JPS57106936A true JPS57106936A (en) 1982-07-03

Family

ID=16137829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18355480A Pending JPS57106936A (en) 1980-12-24 1980-12-24 Interface controlling system

Country Status (1)

Country Link
JP (1) JPS57106936A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120455A (en) * 1983-12-01 1985-06-27 Fujitsu Ltd Bus line controller
FR2641389A1 (en) * 1988-12-30 1990-07-06 Intel Corp METHOD AND COMMUNICATION SYSTEM FOR TRANSMITTING CONFIGURATION INFORMATION FROM A MEMORY MODULE TO A PROCESSOR OF A COMPUTER SYSTEM
US5862375A (en) * 1990-08-31 1999-01-19 Advanced Micro Devices, Inc. System for effecting communications between a computing device and a plurality of peripheral devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120455A (en) * 1983-12-01 1985-06-27 Fujitsu Ltd Bus line controller
FR2641389A1 (en) * 1988-12-30 1990-07-06 Intel Corp METHOD AND COMMUNICATION SYSTEM FOR TRANSMITTING CONFIGURATION INFORMATION FROM A MEMORY MODULE TO A PROCESSOR OF A COMPUTER SYSTEM
US5862375A (en) * 1990-08-31 1999-01-19 Advanced Micro Devices, Inc. System for effecting communications between a computing device and a plurality of peripheral devices

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