JPS57106218A - Cmos type dff circuit - Google Patents

Cmos type dff circuit

Info

Publication number
JPS57106218A
JPS57106218A JP55182290A JP18229080A JPS57106218A JP S57106218 A JPS57106218 A JP S57106218A JP 55182290 A JP55182290 A JP 55182290A JP 18229080 A JP18229080 A JP 18229080A JP S57106218 A JPS57106218 A JP S57106218A
Authority
JP
Japan
Prior art keywords
gate
gates
trs
clocks
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55182290A
Other languages
Japanese (ja)
Other versions
JPH0311125B2 (en
Inventor
Kazuo Yamada
Tsutomu Sumiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55182290A priority Critical patent/JPS57106218A/en
Publication of JPS57106218A publication Critical patent/JPS57106218A/en
Publication of JPH0311125B2 publication Critical patent/JPH0311125B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To execute easily the counter test, by adding a simple input circuit to a D-type flip-flop (DFF) circuit to give the scanning function to it. CONSTITUTION:An inverter I3 and an input gate G3 are provided in parallel with an inverter I1 and an input gate G1 of the data input part, and gates which receive clocks B and B' are added to an output gate G2. Data SDi is inputted in case that this DFF circuit is used as one element (one stage) of a shift register, and the gate G3 of the date input part is switched by clocks A and A'. The output gate G2 consists of P channel MOS transistors (TR) Q1-Q3 and (n) channel MOS TRs Q4-Q6 connected in series, and clocks B and B' are applied to gates of TRs Q1 and Q6, and clocks CK' and CK are applied to gates of TRs Q2 and Q5, and the output of an input latch circuit is applied to gates of TRs Q3 and Q4.
JP55182290A 1980-12-23 1980-12-23 Cmos type dff circuit Granted JPS57106218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182290A JPS57106218A (en) 1980-12-23 1980-12-23 Cmos type dff circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182290A JPS57106218A (en) 1980-12-23 1980-12-23 Cmos type dff circuit

Publications (2)

Publication Number Publication Date
JPS57106218A true JPS57106218A (en) 1982-07-02
JPH0311125B2 JPH0311125B2 (en) 1991-02-15

Family

ID=16115689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182290A Granted JPS57106218A (en) 1980-12-23 1980-12-23 Cmos type dff circuit

Country Status (1)

Country Link
JP (1) JPS57106218A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6189715A (en) * 1984-10-01 1986-05-07 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Electronic flip-flop circuit
JPS6424504A (en) * 1987-07-20 1989-01-26 Sharp Kk Logic circuit device
JPH0282711A (en) * 1988-09-19 1990-03-23 Fujitsu Ltd Transmission gate type flip flop
JPH0736508B2 (en) * 1983-01-25 1995-04-19 スト−リツジ・テクノロジ−・パ−トナ−ズ Logic circuit
JP2008219785A (en) * 2007-03-07 2008-09-18 Sanyo Electric Co Ltd Semiconductor integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5579524A (en) * 1978-12-13 1980-06-16 Fujitsu Ltd Flip-flop circuit
JPS55129772A (en) * 1979-01-23 1980-10-07 Koenemann Bernd Logic block for integrated digital circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5579524A (en) * 1978-12-13 1980-06-16 Fujitsu Ltd Flip-flop circuit
JPS55129772A (en) * 1979-01-23 1980-10-07 Koenemann Bernd Logic block for integrated digital circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736508B2 (en) * 1983-01-25 1995-04-19 スト−リツジ・テクノロジ−・パ−トナ−ズ Logic circuit
JPS6189715A (en) * 1984-10-01 1986-05-07 フィリップス　エレクトロニクス　ネムローゼ　フェンノートシャップ Electronic flip-flop circuit
JPS6424504A (en) * 1987-07-20 1989-01-26 Sharp Kk Logic circuit device
JPH0282711A (en) * 1988-09-19 1990-03-23 Fujitsu Ltd Transmission gate type flip flop
JP2008219785A (en) * 2007-03-07 2008-09-18 Sanyo Electric Co Ltd Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPH0311125B2 (en) 1991-02-15

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