JPS57105038A - Operand processing method of ss-type instruction - Google Patents

Operand processing method of ss-type instruction

Info

Publication number
JPS57105038A
JPS57105038A JP55181584A JP18158480A JPS57105038A JP S57105038 A JPS57105038 A JP S57105038A JP 55181584 A JP55181584 A JP 55181584A JP 18158480 A JP18158480 A JP 18158480A JP S57105038 A JPS57105038 A JP S57105038A
Authority
JP
Japan
Prior art keywords
control part
address
phase
instruction
user instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55181584A
Other languages
Japanese (ja)
Other versions
JPS6341092B2 (en
Inventor
Toshio Iwao
Kazutoshi Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55181584A priority Critical patent/JPS57105038A/en
Publication of JPS57105038A publication Critical patent/JPS57105038A/en
Publication of JPS6341092B2 publication Critical patent/JPS6341092B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To shorten a processing time, by providing a simple controlling circuit, and calculating an address of the first and second operands of an SS-type user instruction for reading both the operands from a memory and storing its operation result in the memory, by use of the same hardward. CONSTITUTION:A user instruction read out frm a main memory 10 is held by an instruction register IR11. As for its user instruction, its instruction type is discriminated in phase ''0'', and if necessary, its address is calculated by the exclusive hardware in phase 1, and the processing corresponding to an OP code is executed by a microprogram in phase 2. Subsequently, the OP code is sent to an address control part 13, and designates an execution start address of the microprogram. Also, an output of the control part 13 is held by an ROM data register 14 through an ROM12, its output is supplied to the control part 15, and the control part 15 outputs control signals such as a set signal SSS, a reset signal RSS, etc.
JP55181584A 1980-12-22 1980-12-22 Operand processing method of ss-type instruction Granted JPS57105038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55181584A JPS57105038A (en) 1980-12-22 1980-12-22 Operand processing method of ss-type instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55181584A JPS57105038A (en) 1980-12-22 1980-12-22 Operand processing method of ss-type instruction

Publications (2)

Publication Number Publication Date
JPS57105038A true JPS57105038A (en) 1982-06-30
JPS6341092B2 JPS6341092B2 (en) 1988-08-15

Family

ID=16103356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55181584A Granted JPS57105038A (en) 1980-12-22 1980-12-22 Operand processing method of ss-type instruction

Country Status (1)

Country Link
JP (1) JPS57105038A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289427A (en) * 1985-06-18 1986-12-19 Panafacom Ltd Access processing system based upon microprogram
USRE40498E1 (en) 1993-05-27 2008-09-09 Matsushita Electric Industrial Co., Ltd. Variable address length compiler and processor improved in address management

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442190U (en) * 1990-08-08 1992-04-09

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289427A (en) * 1985-06-18 1986-12-19 Panafacom Ltd Access processing system based upon microprogram
USRE40498E1 (en) 1993-05-27 2008-09-09 Matsushita Electric Industrial Co., Ltd. Variable address length compiler and processor improved in address management
USRE41959E1 (en) 1993-05-27 2010-11-23 Panasonic Corporation Variable address length compiler and processor improved in address management

Also Published As

Publication number Publication date
JPS6341092B2 (en) 1988-08-15

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