JPS57103432A - Selecting circuit - Google Patents
Selecting circuitInfo
- Publication number
- JPS57103432A JPS57103432A JP18090180A JP18090180A JPS57103432A JP S57103432 A JPS57103432 A JP S57103432A JP 18090180 A JP18090180 A JP 18090180A JP 18090180 A JP18090180 A JP 18090180A JP S57103432 A JPS57103432 A JP S57103432A
- Authority
- JP
- Japan
- Prior art keywords
- logical
- switches
- circuits
- ffs
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
Landscapes
- Electronic Switches (AREA)
Abstract
PURPOSE:To set and reset a selecting signal only by the operation of a momentary switch, by constituting a circuit with plural momentary switches and logical operation circuits, OR gates, and FFs corresponding to these momentary switches. CONSTITUTION:A circuit consists of momentary switches 1a-1n and logical operation circuits 23a-23n, OR circuits 21a-21n, and FFs 22a-22n corresponding to switches 1a-1n, and signals from all switches 1a-1n and outputs of FFs corresponding to logical operation circuits are inputted to circuits 23a-23n. FFs are inverted when outputs of OR circuits are logical 1, and OR signals of input signals from switches are outputted only when signals of output terminals 3a-3n of FFs are logical 1. For example, when terminals 3b and 3a are logical 1 and 0, respectively, depression of the switch 1a inverts the FF22a to set terminals 3a and 3b logical 1 and 0 respectively. When the terminal 3a is logical 1 and all other terminals are logical 0, depression of the switch 1a outputs the logical 1 from the circuit 21a and inverts the FF22a, and the terminal 3a becomes logical 0, and the state of other terminals is not changed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18090180A JPS57103432A (en) | 1980-12-18 | 1980-12-18 | Selecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18090180A JPS57103432A (en) | 1980-12-18 | 1980-12-18 | Selecting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57103432A true JPS57103432A (en) | 1982-06-28 |
Family
ID=16091285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18090180A Pending JPS57103432A (en) | 1980-12-18 | 1980-12-18 | Selecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57103432A (en) |
-
1980
- 1980-12-18 JP JP18090180A patent/JPS57103432A/en active Pending
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