JPS57101926A - Data transferring circuit - Google Patents
Data transferring circuitInfo
- Publication number
- JPS57101926A JPS57101926A JP17825380A JP17825380A JPS57101926A JP S57101926 A JPS57101926 A JP S57101926A JP 17825380 A JP17825380 A JP 17825380A JP 17825380 A JP17825380 A JP 17825380A JP S57101926 A JPS57101926 A JP S57101926A
- Authority
- JP
- Japan
- Prior art keywords
- data
- input
- outputting
- output part
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To execute a transfer with high reliability without extending a transfer line even when the quantity of transfer data has increased, by dividing the data into data, address data and a control signal, and transferring each data by means of time division. CONSTITUTION:A control part 1 transfers data to be transferred to an operation part 51, to an input/output part 21, by outputting data to be transferred to a data bus (a), outputting an address for selecting the input/output part 21, to an address bus (b), and outputting a control signal to a control line (c). In this case, the control part 1 transfers address data to an input/output part 22, by outputting address data to an input/output part 41 of the operation part 51, outputting an address for selecting the input/output part 22, to the bus (b), and outputting the control signal to the line (c). Moreover, the control part 1 outputs a control signal to a control line to the input/output part 41 of the operation part 1, and transfers the control signal to an input/output part 23. In this way, data is transferred to the input/output part 41 and the operation part 51. In this regard, data of an operation part 52-5n is also transferred in the same way.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17825380A JPS57101926A (en) | 1980-12-16 | 1980-12-16 | Data transferring circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17825380A JPS57101926A (en) | 1980-12-16 | 1980-12-16 | Data transferring circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57101926A true JPS57101926A (en) | 1982-06-24 |
Family
ID=16045256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17825380A Pending JPS57101926A (en) | 1980-12-16 | 1980-12-16 | Data transferring circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57101926A (en) |
-
1980
- 1980-12-16 JP JP17825380A patent/JPS57101926A/en active Pending
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