JPS57100545A - Debug device - Google Patents
Debug deviceInfo
- Publication number
- JPS57100545A JPS57100545A JP55177786A JP17778680A JPS57100545A JP S57100545 A JPS57100545 A JP S57100545A JP 55177786 A JP55177786 A JP 55177786A JP 17778680 A JP17778680 A JP 17778680A JP S57100545 A JPS57100545 A JP S57100545A
- Authority
- JP
- Japan
- Prior art keywords
- address
- conversion
- information
- supplied
- relative
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To carry out an automatic conversion or its adverse conversion between an absolute address and the relative address of each module, by adding an address arithmetic function to a debug device. CONSTITUTION:Each name of a program module, the discrimination for ROM or RAM plus a relative address of the ROM and RAM are supplied through an input part 12. This information is supplied to a control circuit part 18 through an input interface circuit 19. In this case, the supplied relative address is converted into an absolute address at the part 18 by means of an address arithmetic function of an address arithmetic circuit part 17. Both the information before conversion and the information after conversion are fed to a display output part 16 via an input interface circuit 14. At the same time, the information obtained after the simulation of a system 15 applying a computer is displayed at the part 16 in the forms of both the absolute and relative addresses.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55177786A JPS57100545A (en) | 1980-12-15 | 1980-12-15 | Debug device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55177786A JPS57100545A (en) | 1980-12-15 | 1980-12-15 | Debug device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57100545A true JPS57100545A (en) | 1982-06-22 |
Family
ID=16037073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55177786A Pending JPS57100545A (en) | 1980-12-15 | 1980-12-15 | Debug device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57100545A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63311449A (en) * | 1987-06-12 | 1988-12-20 | Nec Corp | Abort dump processing system |
JPS63318643A (en) * | 1987-06-22 | 1988-12-27 | Yokogawa Hewlett Packard Ltd | Address display system |
-
1980
- 1980-12-15 JP JP55177786A patent/JPS57100545A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63311449A (en) * | 1987-06-12 | 1988-12-20 | Nec Corp | Abort dump processing system |
JPS63318643A (en) * | 1987-06-22 | 1988-12-27 | Yokogawa Hewlett Packard Ltd | Address display system |
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