JPS5698874A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5698874A JPS5698874A JP42380A JP42380A JPS5698874A JP S5698874 A JPS5698874 A JP S5698874A JP 42380 A JP42380 A JP 42380A JP 42380 A JP42380 A JP 42380A JP S5698874 A JPS5698874 A JP S5698874A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrodes
- source
- platinum
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE: To simplify the preparation process of the FETs, by making the gate, source and drain electrodes with the use of platinum silicides made in the presence of polycrystlal or amorphous Si and by making the wires that extend from the said electrodes by the same process on the same layer.
CONSTITUTION: On the P type semiconductor substrate 31, the device separation layer 32, the P+ type region 33 as the channel stopper and the N+ type layers 34a, 34b and 34c which correspond to the source and drain regions are formed, and the N type layer 35 is further formed as the active layer. Next, the part where the gate electrodes 36a and 36b of Schottky junction border on the layer 35 and the part where the ohmic electrodes 36c, 36d and 36b of source and drain regions border on the layer 34b are formed. These are made of platinum silicide consisting of polycrystal or amorphous Si. On the platinum silicide, metal such as W1 and Mo are preliminerily placed that is not platinum itself and whose alloy temperature is high enough. Thus the resistance is minimized, resulting in the high velocity of IC.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP42380A JPS5698874A (en) | 1980-01-07 | 1980-01-07 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP42380A JPS5698874A (en) | 1980-01-07 | 1980-01-07 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5698874A true JPS5698874A (en) | 1981-08-08 |
| JPS6243552B2 JPS6243552B2 (en) | 1987-09-14 |
Family
ID=11473386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP42380A Granted JPS5698874A (en) | 1980-01-07 | 1980-01-07 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5698874A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274359A (en) * | 1985-04-01 | 1986-12-04 | フエアチヤイルド セミコンダクタ コ−ポレ−シヨン | Small contactless ram cell |
| JPH07221096A (en) * | 1994-01-24 | 1995-08-18 | Lg Semicon Co Ltd | Silicide plug formation |
| JPH08227901A (en) * | 1995-02-20 | 1996-09-03 | Nec Corp | Fabrication of semiconductor device |
| JP4912886B2 (en) * | 2003-11-24 | 2012-04-11 | トライクウィント セミコンダクター，インコーポレーテッド | Monolithic integrated enhancement mode and depletion mode FET and method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0515898Y2 (en) * | 1987-01-30 | 1993-04-26 |
-
1980
- 1980-01-07 JP JP42380A patent/JPS5698874A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274359A (en) * | 1985-04-01 | 1986-12-04 | フエアチヤイルド セミコンダクタ コ−ポレ−シヨン | Small contactless ram cell |
| JPH07221096A (en) * | 1994-01-24 | 1995-08-18 | Lg Semicon Co Ltd | Silicide plug formation |
| JPH08227901A (en) * | 1995-02-20 | 1996-09-03 | Nec Corp | Fabrication of semiconductor device |
| JP2687917B2 (en) * | 1995-02-20 | 1997-12-08 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP4912886B2 (en) * | 2003-11-24 | 2012-04-11 | トライクウィント セミコンダクター，インコーポレーテッド | Monolithic integrated enhancement mode and depletion mode FET and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6243552B2 (en) | 1987-09-14 |
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