JPS5693350A - Armor of semiconductor device - Google Patents

Armor of semiconductor device

Info

Publication number
JPS5693350A
JPS5693350A JP17370079A JP17370079A JPS5693350A JP S5693350 A JPS5693350 A JP S5693350A JP 17370079 A JP17370079 A JP 17370079A JP 17370079 A JP17370079 A JP 17370079A JP S5693350 A JPS5693350 A JP S5693350A
Authority
JP
Japan
Prior art keywords
layer
overvoltage
substance
terminals
outside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17370079A
Other languages
Japanese (ja)
Inventor
Tetsuo Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17370079A priority Critical patent/JPS5693350A/en
Publication of JPS5693350A publication Critical patent/JPS5693350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To protect IC by a method wherein a substance which absorbs and reduces an overvoltage from the outside is inserted between a terminals and ground or terminals. CONSTITUTION:A diode 4 is surrounded by a primary protective layer 3, then covered on the whole with a metal oxide compound or a resistive substance 2 having a suitable conductivity, and furthermore, coated with an electrical insulator 1 such as plastics permitting electricity to be commutated and glass. The layer 3 is chemically inactive and prevents an element 4 from being influenced from the outside and is formed for specical use. Terminals 4a, 4b are attached to the element and led to the outside through layer 1-3. Otherwise, a terminal 5 is allowed to be let out of the layer 2. If the overvoltage is applied, the protective layer 2 absrobs and reduces the same so that the element 4 is not influenced inside. When the excess voltage is removed, the layer 2 returns to be in the original state and all energies of the overvoltage effect increase of a temperature of the substance. A well-known substance having ZnO, SiC as the principal component is used. With this strcuture, a device of a large overvoltage withstand value can be obtained.
JP17370079A 1979-12-26 1979-12-26 Armor of semiconductor device Pending JPS5693350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17370079A JPS5693350A (en) 1979-12-26 1979-12-26 Armor of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17370079A JPS5693350A (en) 1979-12-26 1979-12-26 Armor of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5693350A true JPS5693350A (en) 1981-07-28

Family

ID=15965494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17370079A Pending JPS5693350A (en) 1979-12-26 1979-12-26 Armor of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5693350A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01273344A (en) * 1988-04-25 1989-11-01 Matsushita Electric Ind Co Ltd Semiconductor device
JPH03102747U (en) * 1990-02-09 1991-10-25
CN105552056A (en) * 2016-02-03 2016-05-04 泰州优宾晶圆科技有限公司 Silver-faced high-voltage planar MOS schottky diode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01273344A (en) * 1988-04-25 1989-11-01 Matsushita Electric Ind Co Ltd Semiconductor device
JPH03102747U (en) * 1990-02-09 1991-10-25
CN105552056A (en) * 2016-02-03 2016-05-04 泰州优宾晶圆科技有限公司 Silver-faced high-voltage planar MOS schottky diode

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