JPS5690629A - Count number reading system - Google Patents

Count number reading system

Info

Publication number
JPS5690629A
JPS5690629A JP16695179A JP16695179A JPS5690629A JP S5690629 A JPS5690629 A JP S5690629A JP 16695179 A JP16695179 A JP 16695179A JP 16695179 A JP16695179 A JP 16695179A JP S5690629 A JPS5690629 A JP S5690629A
Authority
JP
Japan
Prior art keywords
input pin
input
whole
clock
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16695179A
Other languages
Japanese (ja)
Other versions
JPS627737B2 (en
Inventor
Kikuo Shiraishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16695179A priority Critical patent/JPS5690629A/en
Publication of JPS5690629A publication Critical patent/JPS5690629A/en
Publication of JPS627737B2 publication Critical patent/JPS627737B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H03K21/12—Output circuits with parallel read-out

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent a count miss even if input operation and read operation collide mutually, by shifting the timing of supplying a pulse input to be counted to a counter on the whole with a shift clock of a frequency higher than that of the input. CONSTITUTION:Spurious input Pin' obtained by shifting input Pin by prescribed extent on the whole is obtained by utilizing D type flip-flop 41. Assuming that input Pin arrives, spurious pulse input Pin' to be counted is obtained being shifted on the whole with shift clock SC. Clock SC has a higher frequency that the predicted maximum frequency of input Pin and this input Pin' is slightly out of phase with real input Pin. The pulse width is greater than the period of clock SC by integer times, but the appearance of input Pin is reproduced accurately.
JP16695179A 1979-12-24 1979-12-24 Count number reading system Granted JPS5690629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16695179A JPS5690629A (en) 1979-12-24 1979-12-24 Count number reading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16695179A JPS5690629A (en) 1979-12-24 1979-12-24 Count number reading system

Publications (2)

Publication Number Publication Date
JPS5690629A true JPS5690629A (en) 1981-07-22
JPS627737B2 JPS627737B2 (en) 1987-02-19

Family

ID=15840642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16695179A Granted JPS5690629A (en) 1979-12-24 1979-12-24 Count number reading system

Country Status (1)

Country Link
JP (1) JPS5690629A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209313A2 (en) * 1985-07-15 1987-01-21 Rca Corporation Clock synchronization circuit for a timer
EP0258458A1 (en) * 1986-03-03 1988-03-09 Fanuc Ltd. Counting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0209313A2 (en) * 1985-07-15 1987-01-21 Rca Corporation Clock synchronization circuit for a timer
EP0258458A1 (en) * 1986-03-03 1988-03-09 Fanuc Ltd. Counting circuit

Also Published As

Publication number Publication date
JPS627737B2 (en) 1987-02-19

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