JPS5687965A - Fsk signal demodulation circuit - Google Patents
Fsk signal demodulation circuitInfo
- Publication number
- JPS5687965A JPS5687965A JP16499579A JP16499579A JPS5687965A JP S5687965 A JPS5687965 A JP S5687965A JP 16499579 A JP16499579 A JP 16499579A JP 16499579 A JP16499579 A JP 16499579A JP S5687965 A JPS5687965 A JP S5687965A
- Authority
- JP
- Japan
- Prior art keywords
- input
- fsk signal
- output
- interruption
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/156—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width
- H04L27/1563—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width using transition or level detection
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To enable to demodulate a FSK signal with a simple adjustment, by counting the clock signal with the pulse having the density according to the frequency of FSK signal and obtaining the output of level according to the result of operation with the reference value in the memory. CONSTITUTION:A FSK signal (a) input to a limiter amplifier 1 is input to a differentiating circuit 5 as a rectangular wave b. The differentiation output c is input to a microprocessor 6, this is received at an interruption input section 6a and the interruption signal is input to the operation section 6d. The operation section 6d reads out the content of the counter 6b counting the clock from the clock source 6c every input of interruption and resets the counter 6b after that. Next, the data of ROM 6e is read out for subtraction, and the flip flop 6f is set to high or low depending on the positive or negative value of the result. Thus, the demodulated output being the output (d) of the flip flop 6f is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16499579A JPS5687965A (en) | 1979-12-19 | 1979-12-19 | Fsk signal demodulation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16499579A JPS5687965A (en) | 1979-12-19 | 1979-12-19 | Fsk signal demodulation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5687965A true JPS5687965A (en) | 1981-07-17 |
Family
ID=15803834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16499579A Pending JPS5687965A (en) | 1979-12-19 | 1979-12-19 | Fsk signal demodulation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5687965A (en) |
-
1979
- 1979-12-19 JP JP16499579A patent/JPS5687965A/en active Pending
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